DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Amendment
Claim 18 is amended.
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks Made in an Amendment, filed 07/16/2026, with respect to the rejection(s) of claim(s) 1-20 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ker et al. U.S. Patent Application 2009/0021872 (hereinafter “Ker”) and Wang U.S. Patent Application 2021/0050341 (hereinafter “Wang”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 4, 10, 11, 13-15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ker and further in view of Wang.
Regarding claim 1, Ker teaches a device (i.e. ESD protection circuit 110)(fig.11), comprising :a first supply rail (i.e. VDD)(fig.11); a second supply rail (i.e. VSS)(fig.11); an input/output terminal (i.e. I/O pad)(fig.1); an electrostatic discharge protection device (i.e. second discharging component 94)(fig.11) coupled between the input/output terminal and a first one of the first supply rail or the second supply rail (implicit); and a trigger circuit (i.e. resistor R1 and capacitor C1)(fig.11) coupled to the first supply rail and the second supply rail (implicit) and configured to: detect an electrostatic discharge event at the input/output terminal based on a voltage of the first supply rail or a voltage of the second supply rail (refer to [0057]), ands witch on the electrostatic discharge protection device in response to detecting the electrostatic discharge event (refer to [0057]); however, Ker does not teach the electrostatic discharge protection device comprising at least two stacked transistors. However, Wang teaches the electrostatic discharge protection device comprising at least two stacked transistors (refer to transistors T4 and T5)(fig.5)(refer also to [0045]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify device of Ker to include the stacked transistors of Wang to provide the advantage of increasing the withstand voltage of the clamp.
Regarding claim 4, Ker and Wang teach the device of claim 1, wherein the electrostatic discharge protection device comprises at least two further stacked transistors (refer to Ker first discharging component 92)(fig.11)(refer also to Wang transistors T4 and T5)(fig.5)(refer also to Wang [0045]) coupled between the input/output terminal and a second one of the first supply rail or the second supply rail (implicit)(refer to Ker first discharging component 92)(fig.11).
Regarding claim 10, Ker and Wang teach the device of claim 1, wherein the trigger circuit comprises a detection circuit configured to generate a detection signal indicative of the electrostatic discharge event (implicit)(refer to Ker resistor R1 and capacitor C1)(fig.11)(refer also to Ker [0057]).
Regarding claim 11, Ker and Wang teach the device of claim 10, wherein the detection circuit comprises a voltage divider circuit (refer to Ker resistor R1 and capacitor C1)(fig.11)(refer also to Ker [0057]) coupled between the first and second supply rails (implicit)(refer to Ker fig.11), wherein an output of the voltage divider circuit is configured to provide the detection signal (refer to Ker [0057] and fig.11).
Regarding claim 13, Ker and Wang teach the device of claim 10, wherein the detection circuit comprises an RC filter circuit (i.e. Ker resistor R1 and capacitor C1)(fig.11) coupled between the first and second supply rails (implicit)(refer to Ker fig.11), wherein an output of the RC filter circuit is configured to provide the detection signal (refer to Ker [0057] and fig.11).
Regarding claim 14, Ker and Wang teach the device of claim 10, further comprising an amplifier circuit (i.e. Ker inverters INV_1, INV_2, and INV_3)(fig.11) configured to amplify the detection signal to generate a control signal for the electrostatic discharge protection device (implicit).
Regarding claim 15, Ker and Wang teach the device of claim 14, wherein the amplifier circuit comprises one or more inverter stages (implicit)(refer to Ker inverters INV_1, INV_2, and INV_3)(fig.11).
Regarding claim 18, Ker teaches a device (i.e. ESD protection circuit 110)(fig.11), comprising :a first supply rail (i.e. VDD)(fig.11); a second supply rail (i.e. VSS)(fig.11); an input/output terminal (i.e. I/O pad)(fig.1); an electrostatic discharge protection device (i.e. second discharging component 94)(fig.11) coupled between the input/output terminal and a first one of the first supply rail or the second supply rail (implicit); a detection circuit (i.e. resistor R1 and capacitor C1)(fig.11) coupled to the first supply rail and the second supply rail (implicit) and configured to: detect an electrostatic discharge event at the input/output terminal based on a voltage of the first supply rail or a voltage of the second supply rail (refer to [0057]), and generate a detection signal in response to detecting the electrostatic discharge event (refer to [0057]); and an amplifier circuit (i.e. Ker inverters INV_1, INV_2, and INV_3)(fig.11) configured to amplify the detection signal to generate a control signal for the electrostatic discharge protection device (implicit), wherein the control signal is configured to switch on the electrostatic discharge protection switch in response to the detection circuit detecting the electrostatic discharge event (refer to [0057]); however, Ker does not teach the electrostatic discharge protection device comprising at least two stacked transistors. However, Wang teaches the electrostatic discharge protection device comprising at least two stacked transistors (refer to transistors T4 and T5)(fig.5)(refer also to [0045]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify device of Ker to include the stacked transistors of Wang to provide the advantage of increasing the withstand voltage of the clamp.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ker and Wang as applied to claim 1 above, and further in view of Voldman U.S. Patent No. 6,369,994 (hereinafter “Voldman”).
Regarding claim 8, Ker and Wang teach the device of claim 1; however, they do not teach the device further comprising: a first electrostatic discharge protection element coupled between a first node coupled to the input/output terminal and the first supply rail; and a second electrostatic discharge protection element coupled between the first node and the second supply rail, wherein the electrostatic discharge protection device is coupled between a second node coupled to the input/output terminal and the one of the first supply rail or the second supply rail, and the first node is between the input/output terminal and the second node. However, Voldman teaches the device further comprising: a first electrostatic discharge protection element (i.e. SOI diode 31)(fig.10) coupled between a first node coupled to the input/output terminal and the first supply rail (implicit); and a second electrostatic discharge protection element (i.e. SOI diode 32)(fig.10) coupled between the first node and the second supply rail (implicit), wherein the electrostatic discharge protection device (i.e. transistors 92 or 93)(fig.10) coupled between a second node coupled to the input/output terminal and the one of the first supply rail or the second supply rail (implicit), and the first node is between the input/output terminal and the second node (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ker and Wang to include the first and second electrostatic discharge protection elements of Voldman to provide the advantage of increasing the ESD protection of the device with a faster device to discharge the ESD before the electrostatic discharge protection device turns on.
Regarding claim 9, Ker, Wang, and Voldman teach the device of claim 8, further comprising a current limiting element (i.e. Voldman resistor R94)(fig.10) coupled between the first node and the second node (implicit).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ker and Wang as applied to claim 11 above, and further in view of Chao et al. U.S. Patent Application 2021/0135451 (hereinafter “Chao”).
Regarding claim 12, Ker and Wang teach the device of claim 11; however, they do not teach wherein the voltage divider circuit comprises at least one diode in series with a resistor, wherein the output of the voltage divider circuit is at a node between the at least one diode and the resistor. However, Chao teaches wherein the voltage divider circuit comprises at least one diode (i.e. diodes D1-Dm)(fig.4) in series with a resistor (i.e. impedance element Z)(fig.4)(refer also to [0025]), wherein the output of the voltage divider circuit is at a node between the at least one diode and the resistor (refer to figure 4 and [0025]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ker and Wang to include the voltage divider of Chao to provide the advantage of using a common, well-known, alternative ESD detection circuit.
Claim(s) 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng as applied to claims 15 and 18 above, and further in view of Zhu et al. U.S. Patent Application 2023/0007947 (hereinafter “Zhu”).
Regarding claim 16, Ker and Wang teach the device of claim 15; however, they do not teach wherein each inverter stage comprises: a first pair of stacked transistors coupled between the first supply rail and an output node of the respective inverter stage; and a second pair of stacked transistors coupled between the output node of the respective inverter stage and the second supply rail. However, Zhu teaches wherein each inverter stage comprises: a first pair of stacked transistors (i.e. transistors N11 and N12)(fig.6) coupled between the first supply rail (i.e. VSS)(fig.6) and an output node of the respective inverter stage (i.e. output node in the figure below)(fig.6); and a second pair of stacked transistors (i.e. transistors P11 and P12)(fig.6) coupled between the output node of the respective inverter stage and the second supply rail (i.e. VDD)(fig.6). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ker and Wang to include the inverter structure of Zhu to provide the advantage of providing an inverter able to handle the voltages of the device with high voltage gain and better isolation.
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Regarding claim 19, Ker and Wang teach the device of claim 18, wherein the amplifier circuit comprises one or more inverter stages (refer to Ker inverters INV_1, INV_2, and INV_3)(fig.11); however, they do not teach wherein each inverter stage comprises: a first pair of stacked transistors coupled between the first supply rail and an output node of the respective inverter stage; and a second pair of stacked transistors coupled between the output node of the respective inverter stage and the second supply rail. However, Zhu teaches wherein each inverter stage comprises: a first pair of stacked transistors (i.e. transistors N11 and N12)(fig.6) coupled between the first supply rail (i.e. VSS)(fig.6) and an output node of the respective inverter stage (i.e. output node in the figure above)(fig.6); and a second pair of stacked transistors (i.e. transistors P11 and P12)(fig.6) coupled between the output node of the respective inverter stage and the second supply rail (i.e. VDD)(fig.6). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ker and Wang to include the inverter structure of Zhu to provide the advantage of providing an inverter able to handle the voltages of the device with high voltage gain and better isolation.
Allowable Subject Matter
Claim 2, 3, 5-7, 17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 2 and 3 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 2, especially wherein: the at least two stacked transistors comprise a first transistor controlled by the trigger circuit and a second transistor; and the device further comprises a bias circuit configured to bias a control terminal of the second transistor to a predefined voltage value. Claim 3 is indicated as containing allowable subject matter based on its dependency on claim 2. Claims 5-7 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially wherein: the at least two stacked transistors comprise a first transistor controlled by the trigger circuit and a second transistor; the device further comprises a bias circuit configured to bias a control terminal of the second transistor to a predefined voltage value; the at least two further stacked transistors comprise a first further transistor controlled by the trigger circuit and a second further transistor; and the bias circuit is further configured to bias a control terminal of the second further transistor to a further predefined voltage value. Claims 6 and 7 are indicated as containing allowable subject matter based on their dependency on claim 5. Claim 17 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 17, especially wherein: the at least two stacked transistors comprise a first transistor controlled by the trigger circuit and a second transistor; the device further comprises a bias circuit configured to bias a control terminal of the second transistor to a predefined voltage value; the at least two further stacked transistors comprise a first further transistor controlled by the trigger circuit and a second further transistor; the bias circuit is further configured to bias a control terminal of the second further transistor to a further predefined voltage value; the at least two stacked transistors are coupled between the input/output terminal and the first supply rail; the at least two further stacked transistors are coupled between the input/output terminal and the second supply rail; a first transistor of the first pair and a first transistor of the second pair are coupled to an input node of the respective inverter stage; and the bias circuit is configured to: bias a control terminal of a second transistor of the first pair to the predefined voltage value, and bias a control terminal of a second transistor of the second pair to the further predefined voltage value. Claim 20 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 20, especially a bias circuit, wherein: a first transistor of the first pair and a first transistor of the second pair are coupled to an input node of the respective inverter stage; and the bias circuit is configured to: bias a control terminal of a second transistor of the first pair to a first predefined voltage, and bias a control terminal of a second transistor of the second pair to a second predefined voltage.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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