Prosecution Insights
Last updated: October 02, 2026
Application No. 18/931,804

CAPACITOR

Non-Final OA §102§103
Filed
Oct 30, 2024
Priority
May 13, 2022 — JP 2022-079550 +1 more
Examiner
SINCLAIR, DAVID M
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
867 granted / 1267 resolved
+8.4% vs TC avg
Strong +20% interview lift
Without
With
+19.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
50 currently pending
Career history
1305
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
52.4%
+12.4% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1267 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Email Communication Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 6, & 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yook et al. (US 2020/0137889). In regards to claim 1, Yook ‘889 discloses A capacitor, comprising: a capacitor layer including a first electrode layer (100 and/or 110 on surfaces 100a/100b – fig. 2; [0036-0037]) and a second electrode layer (130 on surfaces 100a/100b – fig. 2; [0036]) facing each other in a thickness direction with a dielectric layer (120 on surfaces 100a/100b – fig. 2; [0036]) interposed therebetween; and a coaxial through-hole conductor penetrating through the capacitor layer in the thickness direction, wherein the coaxial through-hole conductor includes: a first through-hole conductor (110 extending through 101 – fig. 2; [0036]) electrically coupled to an end surface of the first electrode layer; and a second through-hole conductor (130 extending through 101 – fig. 2; [0036]) inside the first through-hole conductor and electrically coupled to the second electrode layer, wherein the first through-hole conductor and the second through-hole conductor are insulated from each other (fig. 2 – 120 is between 110 & 130). In regards to claim 2, Yook ‘889 discloses The capacitor according to Claim 1, further comprising a sealing layer (150 – fig. 2; [0042]) that seals the capacitor layer. In regards to claim 3, Yook ‘889 discloses The capacitor according to Claim 2, further comprising an inner wiring layer (110 on surfaces 100a/100b & portion of 141 extending through 150 – fig. 2; [0036] & [0040) inside the sealing layer, wherein the first electrode layer (100 – fig. 2; [0036-0037]) is electrically extended to a surface of the sealing layer via the first through-hole conductor and the inner wiring layer (fig. 2). In regards to claim 6, Yook ‘889 discloses The capacitor according to Claim 1, further comprising an insulating layer (120 extending through 101 – fig. 2; [0036]) around the first through-hole conductor. In regards to claim 12, Yook ‘889 discloses The capacitor according to Claim 1, wherein a space between the first through-hole conductor and the second through-hole conductor is filled with an insulating material (120 extending through 101 – fig. 2; [0036]). In regards to claim 13, Yook ‘889 discloses The capacitor according to Claim 1, wherein an axis of the second through-hole conductor coincides with an axis of the first through-hole conductor (fig. 2). Claim(s) 1-6 & 9-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2009/0161298). In regards to claim 1, Lee ‘298 discloses A capacitor, comprising: a capacitor layer including a first electrode layer (112- fig. 6; [0026]) and a second electrode layer (114- fig. 6; [0026]) facing each other in a thickness direction with a dielectric layer (116- fig. 6; [0026]) interposed therebetween; and a coaxial through-hole conductor penetrating through the capacitor layer in the thickness direction, wherein the coaxial through-hole conductor includes: a first through-hole conductor (122 and/or 130 – fig. 6; [0024]) electrically coupled to an end surface of the first electrode layer; and a second through-hole conductor (126 and/or 128 – fig. 6; [0023]) inside the first through-hole conductor and electrically coupled to the second electrode layer, wherein the first through-hole conductor and the second through-hole conductor are insulated from each other (fig. 2 & 6; [0024]). In regards to claim 2, Lee ‘298 discloses The capacitor according to Claim 1, further comprising a sealing layer (530 – fig. 6; [0033]) that seals the capacitor layer. In regards to claim 3, Lee ‘298 discloses The capacitor according to Claim 2, further comprising an inner wiring layer (portion of 122 on bottom surface of 100 and 140 – fig. 2; [0023]) inside the sealing layer, wherein the first electrode layer is electrically extended to a surface of the sealing layer via the first through-hole conductor and the inner wiring layer (fig. 2). In regards to claim 4, Lee ‘298 discloses The capacitor according to Claim 3, wherein the second through-hole conductor penetrates through both the capacitor layer and the sealing layer in the thickness direction (fig. 2 & 6). In regards to claim 5, Lee ‘298 discloses The capacitor according to Claim 2, wherein the second through-hole conductor penetrates through both the capacitor layer and the sealing layer in the thickness direction (fig. 2 & 6). In regards to claim 6, Lee ‘298 discloses The capacitor according to Claim 1, further comprising an insulating layer (124 – fig. 2; [0023]) around the first through-hole conductor. In regards to claim 9, Lee ‘298 discloses The capacitor according to Claim 1, wherein the capacitor layer has two or more capacitance effective portions and an insulation partitioning portion that partitions the capacitance effective portions when viewed from the thickness direction (fig. 6-7; [0035] – element 530 is an insulation partitioning portion). In regards to claim 10, Lee ‘298 discloses The capacitor according to Claim 9, wherein at least one of the coaxial through-hole conductor is inside the capacitance effective portion (fig. 6-7). In regards to claim 11, Lee ‘298 discloses The capacitor according to Claim 1, wherein a width of the first through-hole conductor is smaller than a width of the second through-hole conductor (fig. 2 & 6). In regards to claim 12, Lee ‘298 discloses The capacitor according to Claim 1, wherein a space between the first through-hole conductor and the second through-hole conductor is filled with an insulating material (124 – fig. 2; [0023]). In regards to claim 13, Lee ‘298 discloses The capacitor according to Claim 1, wherein an axis of the second through-hole conductor coincides with an axis of the first through-hole conductor (fig. 2 & 6). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yook ‘889 in view of Wu et al. (US 2009/0159322). In regards to claim 7, Yook ‘889 fails to disclose wherein the first electrode layer is an anode plate including a core portion made of a metal and a porous portion on at least one main surface of the core portion, the dielectric layer is on a surface of the porous portion, and the second electrode layer is a cathode layer on a surface of the dielectric layer. Wu ‘322 discloses wherein the first electrode layer is an anode plate including a core portion (202 – fig. 2; [0025]) made of a metal and a porous portion (214 – fig. 2; [0025]) on at least one main surface of the core portion, the dielectric layer (204 – fig. 2; [0025]) is on a surface of the porous portion, and the second electrode layer is a cathode layer (206 – fig. 2; [0025]) on a surface of the dielectric layer. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the electrodes of Yook ‘889 using a porous structure and materials as taught by Wu ‘322 to obtain an increased capacitance and low leakage current. In regards to claim 8, Yook ‘889 as modified by Wu ‘322 further disclose wherein the cathode layer includes a solid electrolyte layer on the surface of the dielectric layer ([0025-0026] of Wu ‘322). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yook ‘889 in view of Ida et al. (US 2009/0095511). In regards to claim 14, Yook ‘889 discloses wherein an inside of the second through-hole conductor is filled with a dielectric material (150 – fig. 2; [0042]). Yook ‘889 fails to explicitly disclose the dielectric material containing a resin. Ida ‘511 discloses epoxy used to fill a through hole conductor and cover electrode layers (fig. 8 & 10; [0100] & [0111-0112]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the protecting layer of Yook ‘889 using a resin as taught by Ida ‘511 to ensure good protection and based on the materials available during manufacturing. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2020/0051749 – fig. 3A US 2002/0017399 – fig. 8; [0050] US 2016/0088731 – fig. 2-3 Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY J DOLE can be reached at (571)272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David M Sinclair/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Oct 30, 2024
Application Filed
Aug 18, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
88%
With Interview (+19.5%)
2y 6m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1267 resolved cases by this examiner. Grant probability derived from career allowance rate.

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