DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to amendment filed on 07/24/2026. Claims 1-2, 4, 6, and 8-9 are pending.
Response to Arguments
Applicant asserted on page 12 regarding rejection under 35 U.S.C. 101 “Applicant notes with appreciation that … the Examiner found that the combination of specialized hardware circuits configured as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASIC) together with the memory limitations (e.g., memory mapping for the Fourier map) successfully integrates the mathematical algorithms into a practical, real-time application … To ensure compliance, currently amended claims 1, 8, and 9 continue to maintain these structural hardware elements - such as at least one processing circuit configured as an FPGA or an ASIC, an input interface circuit, and a memory - which physically execute real-time digital signal processing for a visual image data array of three or more dimensions to control the navigation of an autonomous vehicle. These hardware features physically integrate the mathematical steps into a concrete, technological application. Accordingly, subject matter eligibility under § 101 is fully established, and the withdrawal of this rejection is noted as final.”
Examiner respectfully disagrees because in previous OA dated 05/04/2026 page 2, Examiner identified limitations that overcome the 101 rejection were the plurality of circuitries to perform the claimed function, wherein such combination of circuits amounts more than mere instructions to implement an abstract idea on computer and implementing a judicial exception with a particular machine and also the claim recited the limitation of generating a Fourier map by mapping the Fourier coefficient data into a memory. However, such limitations are removed, and merely recite a circuit configured as FPGA or ASIC, allocating, and accessing memory space at a high level of generality do not integrate the judicial exception into a practical application as such limitation amount to no more than mere instructions to apply the judicial exception using computer component.
Applicant further asserted on page 13, “Applicant has deleted the subdivided circuit terms (such as "a hyper parameter data processing circuit", etc.) from the claims and consolidated all such operations under the unified term "the at least one processing circuit" (or "the processing circuit" in claim 9), configured as an FPGA or ASIC. As discussed in detail in the Section 112(a) response below, this terminology finds clear, direct, and explicit antecedent support from the paragraph which extends from page 24, line 21 to page 25, line 1 of the specification, as filed, which describes hardware units such as an FPGA or ASIC, as well as the paragraph which extends from page 10, lines 16-23, which describes a controller including ‘at least one processor’.”
While Examiner agrees that deleting the subdivided circuit terms would overcome the 112(a) lack of written description as previously set forth. However, there is a lack of written description of the limitation of at least one processing circuit configured as an FPGA or ASIC and further requires executing instructions stored in the memory to perform operations because page 24 line 21 to page 25 line 1 merely describes the term “unit” used in the above described embodiments means a hardware component such as FPGA or ASIC, which seems to be boilerplate language because the described embodiments do not use the generic term “unit”. Page 10 line 16-23 describes a controller including at least one processor, such as a central processing unit (CPU) or a graphics processing unit (GPU), such term “unit” in CPU or GPU. However, CPU and GPU are well established term in the art. Furthermore, beside the description of page 25 regarding the term unit being FPGA or ASIC, the specification fails to describes a controller including at least one processor being an FPGA or ASIC to perform operations of the fast multidimensional partial Fourier transform method.
Applicant further asserted on page 15, “In their place, the amended claims recite that the steps are performed by the single, unified "at least one processing circuit" (or "the processing circuit" in claim 9), which is configured as an FPGA or ASIC. This is fully supported by the paragraph which spans from page 24, line 21 to page 25, line 1, which states that functional components can be implemented as hardware components like an FPGA or ASIC, and paragraph on page 10, lines 16-23, which discloses a controller containing at least one processor (such as a CPU or GPU) for controlling the overall operation.”
Examiner respectfully disagrees because page 24-25 does not state that functional components can be implemented as hardware components like an FPGA or ASIC, but page 24-25 describes “The term “unit” used in the above-described embodiments means software or a hardware component”, such language is interpreted as a definition for the generic term “unit”.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112(a) below.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4, 6, and 8-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 line 4-7 recites “at least one processing circuit configured as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) and a memory storing instructions, wherein the at least one processing circuit executes the instructions to cause the digital signal processing circuit to perform the digital signal processing method”. There is lack of written description for such limitation because the specification fails to provide sufficient description that the at least processing circuit being configured as FPGA or ASIC and execute instructions stored in the memory to perform the claimed operations. Page 10 line 16-23 describes a controller includes at least one processor, such as a CPU or a GPU or the like and control the overall operation of the fast multidimensional partial Fourier transform and page 25 describes “the term ‘unit’ used in the above-described embodiments means software or a hardware component such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). However, such boilerplate language in page 25 merely defines the term “unit”, rather than at least one processor in a controller as described in page 10. Accordingly, the specification fails to provide sufficient description for the at least one processing circuit configured as FPGA or ASIC to perform the claimed function. Claims 8-9 recite similar limitation as described above. Thus, they are rejected for the same reasons.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 4, 6, and 8-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites a method for performing fast multidimensional partial Fourier transform
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites a method comprising: set the plurality of hyperparameter data and converting the visual image data array of three or more dimensions into frequency domain based on the plurality of hyperparameter data by utilizing an energy compression property of the visual image data array of three or more dimensions in the frequency domain, thereby outputting multidimensional Fourier coefficient data for the visual image data array of three or more dimensions, wherein the outputting the multidimensional Fourier coefficient data comprises: generating a Fourier map, which is a visualization map in which Fourier coefficient data for the visual image data array are represented by log amplitudes; skipping digital computation of unnecessary Fourier coefficient data by focusing on nonzero Fourier coefficient data parts, based on that the Fourier coefficient data are 0 except for a portion at a center area of the Fourier map; and applying a multidimensional partial Fourier transform once to an entire input when computing the Fourier coefficient data of the portion at the center area of the Fourier map using the Fourier map, wherein the outputting the multidimensional Fourier coefficient data for the visual image data array of three or more dimensions comprises: when the sizes of the multidimensional output area and the input array change, setting the plurality of hyperparameter data used in the multidimensional partial Fourier transform based on constraints on tolerance data and degree data of a polynomial for polynomial approximation, wherein the setting the plurality of hyperparameter data comprises automatically selecting the plurality of hyperparameter data using a convex optimization based algorithm; wherein the multidimensional output area is represented based on a center and radii of a multidimensional box expressed via a multidimensional matrix in a multidimensional space of three or more dimensions; when the sizes of the multidimensional output area and the input array change, finding Twiddle factors of the multidimensional partial Fourier transform whose oscillation is less than a reference value and decomposing the partial Fourier coefficients using the Twiddle factors into a multidimensional fast Fourier transform of sub-blocks of the input array and matrix multiplication, thereby approximating and processing the multidimensional Fourier coefficient data of the multidimensional partial Fourier transform for the data array of three or more dimensions based on the plurality of hyperparameter data to output approximated multidimensional Fourier coefficient data, wherein the setting the plurality of hyperparameter data comprises: setting multidimensional degree data using unconstrained convex optimization based on the constraints; setting multidimensional divisor data based on a size of an array adapted to store the multidimensional Fourier coefficient data, and the multidimensional degree data; setting multidimensional quotient data based on the size of the array adapted to store the multidimensional Fourier coefficient data, and the multidimensional divisor data; setting multidimensional range tensor data based on the size of the array adapted to store the multidimensional Fourier coefficient data, the multidimensional degree data, and the multidimensional quotient data; and setting optimal parenthesization data for an operation representing the multidimensional Fourier coefficient data using the multidimensional range tensor data, wherein the approximating and processing the multidimensional Fourier coefficient data comprises: generating a first tensor data by performing block decomposition on an array adapted to store the multidimensional Fourier coefficient data based on the multidimensional divisor data and the multidimensional quotient data; converting the first tensor data and the multidimensional range tensor data into a second tensor data by performing sequential tensor data product operations on the first tensor data and the multidimensional range tensor data based on the optimal parenthesization data; converting the second tensor data into a third tensor data by permuting the second tensor data based on the multidimensional degree data; converting the third tensor data into a fourth tensor data by applying a fast Fourier transform to the third tensor data; and performing a dot product operation on the fourth tensor data, to which the fast Fourier transform has been applied, based on the multidimensional divisor data and a multidimensional output area, and outputting an array in which the approximated multidimensional Fourier coefficient data has been stored. Such limitations cover mathematical calculations, relationship, and/or formula (see at least page 20-22 describes mathematical algorithms 1 and 2 to perform the step of setting the plurality of hyperparameter, approximating, and processing multidimensional Fourier coefficients based on the hyperparameters. Also see figures 4-8. See at least page 20-22 describes the computation phrase for steps S420 to S426 includes performing a tensor transform, block decomposition, sequential tensor product operations, permuting, applying FFT, and performing dot product operations. Also see algorithm 2 on page 22 and figures 4-5 and 8, and page 8 line 14-15 describes selecting using a convex optimization-based algorithm, which is a mathematical algorithm. Also see page 13 line 2-3 describes the comparing oscillations of twiddle factor with a reference value, page 9 line 5-8 describes the decomposing the computation of coefficients into matrix multiplication. Also see page 12 line 13-18 describes the multidimensional output area based on a center and radii of a multidimensional box as a matrix, see page 7 for the zero skipping scheme that operate only on non-zero data to avoid unnecessary computation and the Fourier map represented as log amplitudes). Alternatively, generating a Fourier map represented by log amplitude or data under broadest reasonable interpretation cover the limitation being performed by using pen and paper, such that one of ordinary skill in the art can create a map or graph for visualization to represent data. Therefore, the claim includes limitations that fall within the “Mathematical Concepts / Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a digital signal processing method, where the digital signal processing method being performed by a digital signal processing circuit including an input interface circuit, at least one processing circuit configured as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), and a memory storing instructions, wherein the at least one processing circuit executes the instructions to cause the digital signal processing circuit to perform the digital signal processing method to compute digitally data. However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing digital signal data and performing mathematical operations including storing instructions and executing instructions. The claim further recites “to improve a processing speed of the digital signal circuit”, such limitation mere recited as a result of performing the abstract idea as recited in the claim. Moreover, the claim recites “for a visual image data array of three of more dimensions for real-time digital signal processing in an autonomous vehicle” and “controlling navigation of the autonomous vehicle based on the approximated multidimensional Fourier coefficient data, wherein the visual image data array of three or more dimensions represents inputs from the autonomous vehicle”, such limitations are recited at a high level of generality and at most considered as mere generally linking the use of the judicial exception into a technological environment or a field of use, such as navigation of autonomous vehicle based on processed image data. Furthermore, the claim recites a step of inputting the visual image data array of three or more dimensions and inputting sizes of a multidimensional output area and an input array related to the visual image data array of three or more dimensions, where such limitation is at most considered as insignificant extra solution activity (e.g., mere data gathering), and the claim also recites the steps of allocating a search space for a plurality of hyperparameter data based on the sizes of the multidimensional output area and the input array such that a physical space complexity of the memory satisfies an asymptotic upper bound of O(N + M) as a physical hardware constraint, wherein N represents the size of the input array and M represents the size of the multidimensional output area; and accessing the search space for the plurality of hyperparameter data in the memory. However, such steps of memory allocating and accessing are also considered at most as insignificant extra solution activity as the step of allocating and accessing are recited at a high level of generality, wherein the recited memory space constraints are merely a result of performing the abstract idea as explained in specification page 22, wherein the algorithm auto-MPFT provides 3 advantages, one of which is space-optimized so that it requires only the minimum space. In other words, by performing the algorithm recited, it results in a physical memory constraint that is space-optimized. Such element fails to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using component components. The same conclusion is reached in step 2B, i.e., mere instructions to apply an exception on computer components cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of inputting data and input sizes and memory allocating and accessing are considered to be insignificant extra-solution activities in step 2A, and are determined to be well-understood, routine, conventional activities in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network, iv. Storing and retrieving information in memory, and also see Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014, page 352 describes a memory allocation instruction that to specify the size of a memory area. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 2 and 4 further recite limitation of setting the plurality of hyperparameters. Such limitations cover mathematical calculations, relationship, and/or formula (see at least page 9 describes reconstruction of the constraint function based on the Chebyshev polynomial approximation, page 16-18 describes the approximating the constraint function to reconstruct the optimization problem into an unconstrained convex optimization problem and page 19 describes the unconstrainted convex optimization as problem 2 and algorithm 1 illustrates step of setting the hyperparameters through problem 2. Also see steps in figures 4 and 7). The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claims are not patent-eligible under 35 U.S.C 101.
Claim 6 further recites limitation of approximating and computing the multidimensional Fourier coefficients. Such limitations cover mathematical calculations, relationship, and/or formula (see at least page 20-22 describes the computation phrase for steps S420 to S426 includes performing a tensor transform, block decomposition, sequential tensor product operations, permuting, applying FFT, and performing dot product operations. Also see algorithm 2 on page 22 and figures 4-5 and 8). The claims do not recite additional elements that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claims are not patent-eligible under 35 U.S.C 101.
Claims 8-9 recite an apparatus claim and a product claim having similar limitations as claim 1. Thus, they are rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached on (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
