DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/08/2026 has been entered.
Response to Amendment
This office action is responsive to amendment filed on 04/08/2026. Claims 1-2, 4, 6, and 8-9 are pending.
Response to Arguments
Applicant’s arguments, see Remarks page 11, filed on 04/08/2026, with respect to have been fully considered and are persuasive. The rejection under 35 U.S.C. 101 has been withdrawn because the claims are amended to recite a plurality of circuits, such as “a hyper parameter data processing circuit”, “a multidimensional Fourier coefficient data processing circuit”, “a multidimensional degree data processing circuit”, “a multidimensional divisor data processing circuit”, “a multidimensional quotient data processing circuit”, “a multidimensional range tensor data processing circuit”, “an optimal parenthesization data processing circuit”, “a first tensor data generating circuit”, “a second tensor data generating circuit”, “a third tensor data generating circuit”, “a fourth tensor data generating circuit”, “a multidimensional Fourier coefficient data output circuit” to perform the claimed function, thus such combination of circuits together amounts more than mere instructions to implement an abstract idea on computer and implementing a judicial exception with a particular machine. Furthermore, the claim recites limitation that is not characterized as abstract idea under step 2A prong one, such as the step of generating a Fourier map by mapping the Fourier coefficient data into a memory. Accordingly, the claim recites additional elements that would integrate the judicial exception into a practical application under step 2A prong two.
Applicant further asserted on page 15 regarding the 101 analysis that the claim 1 provide technological improvement, such as saving massive amounts of computing power by identifies important information concentrated in certain areas, skipping unnecessary computation, speedup processing by breaking large chunks of data into smaller sub-blocks and uses matrix multiplication to simply the math, and ensure hardware is always running at peak efficiency by using a convex optimization algorithm to automatically adjust its setting (hyperparameter).
Examiner respectfully disagrees because such arguably improvements, are direct consequences of performing the mathematical algorithm, such as concentrated in certain areas of a map, skipping computation of values close to 0, dividing data into smaller sub-blocks and uses matrix multiplication, and a convex optimization algorithm. MPEP 2106.05(a) recites “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements”. Thus, performing mathematical operations alone cannot provide the arguably improvements recited above.
Applicant further asserted on page 16, “under MPEP § 2106.05(a), an improvement is often demonstrated by showing that the claim has a functional benefit over prior art. The claims have been amended to replace generic processors with a specific suite of interconnected circuits, including the hyperparameter data processing circuit, divisor data processing circuit, and tensor data generating circuits. These are not generic computer components; they are specialized hardware units configured to execute a non-conventional DSP pipeline. The problem addressed - real-time processing of 3D visual image arrays for autonomous vehicles - is a technological bottleneck caused by high dimensionality. The solution is the creation and utilization of a Fourier map to identify non-zero frequency portions, allowing the hardware to skip digital computation of unnecessary data. This is an improvement in the functioning of the apparatus itself, as it optimizes hardware resource allocation and memory mapping.”
While examiner agrees that the MPEP 2106.05(a) describes technological improvement for 101 analysis, but MPEP 2106.05(a) also recites “It is important to note, the judicial exception alone cannot provide the improvement.” As explained above, any arguably improvements of optimize hardware resource allocation, is a direct consequence of performing the algorithm of identifying non-zero frequency portions and skip unnecessary operation based on values being closed to 0. In other words, it is not the particular amended circuits that provide the improvement, but it is the particular algorithm that provides any arguably improvement.
Applicant further asserted on page 16-17 stating that the navigation control of an autonomous vehicle is not mere generally linking the use of the judicial exception into a particular technological environment and further compare the Flook case and Diehr.
Examiner respectfully disagrees because the limitation of control navigation of the autonomous vehicle based on the approximated result is not similar to Diehr since in the case of Diehr, the claim recites additional elements of process for molding rubber, such as the steps of installing rubber in a press, closing the mold, constantly measuring the temperature in the mold, and automatically opening the press at the proper time. In contrast, the instant claim merely recite a limitation of controlling navigation of the autonomous vehicle based on the result without details of the controlling process. Accordingly, such limitation is considered as mere generally linking the use of the judicial exception into a particular technological environment.
Applicant further asserted on page 17 that the specific arrangement of automatically selecting hyperparameter, performing block decomposition, and executing sequential tensor data product operations is what achieves the documented 7.6x speed improvement, and such a significant leap in efficiency in the field of autonomous navigation indicates the combination is not well-understood, routine, or conventional.
Examiner respectfully disagrees because such combination of elements are characterized as the abstract idea under step 2A prong one. Thus, even though such combination is novel or not well-understood, routine, or conventional, such combination is still an abstract idea as MPEP 2106.04(I) recite “The Supreme Court’s decisions make it clear that judicial exceptions need not be old or long-prevalent, and that even newly discovered or novel judicial exceptions are still exceptions” and MPEP 2106.05(I) “a claim for a new abstract idea is still an abstract idea”. Furthermore, as explained above, since the combination is considered as judicial exception, such combination alone cannot provide the improvement according to MPEP 2106.05(a).
Applicant also asserted on page 12 that “These amendments are supported by paragraphs 38, 39, and 135-149 as well as Figures 1 through 6 of the subject application”.
First, examiner suggests applicant to use the specification as filed for indication of support, instead of using the specification of the publication. Furthermore, specification page 7 (e.g., [0038-0039]) figure 1 describes the plurality of Fourier map visualize Fourier coefficients, and page 23-26 (e.g., [0135-0149]) describes the step of setting a plurality of hyperparameters and approximating and computing multidimensional Fourier coefficients. However, they do not sufficiently describe the step of generating a Fourier map by mapping the Fourier coefficient into a memory, and the plurality of circuits being recited in the claims. Page 25 at most describes the term “unit” means software or a hardware component, such as FPGA and ASIC at a high level, but it is insufficient support for having a plurality circuits, where each operation being perform by a circuit as required in the amended claims.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112(a) below.
Claim Objections
Claims 1-2, 4, 6 are objected to because of the following informalities:
Claim 1 line 13 “at least one processing circuit” should be “the at least one processing circuit” as antecedently recited.
Dependent claims are also objected for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-2, 4, 6, and 8-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 line 19-21; claim 8 line 16-18; claim 9 line 20-22 recite “generating a Fourier map … by mapping the Fourier coefficient data for the visual image data array into a memory”. The specification fails to provide sufficient disclosure for the step of mapping the Fourier coefficient data into a memory. Figure 1 page 7 illustrates a plurality of Fourier maps 121, 122, and 123 which are visualization maps in which Fourier coefficient data are represented by log amplitudes, but figure 1 page 7 does not describe the step of generating Fourier map by mapping the Fourier coefficient data into a memory.
Claims 1 and 8-9 recite a plurality of circuits, such as “a hyper parameter data processing circuit”, “a multidimensional Fourier coefficient data processing circuit”, “a multidimensional degree data processing circuit”, “a multidimensional divisor data processing circuit”, “a multidimensional quotient data processing circuit”, “a multidimensional range tensor data processing circuit”, “an optimal parenthesization data processing circuit”, “a first tensor data generating circuit”, “a second tensor data generating circuit”, “a third tensor data generating circuit”, “a fourth tensor data generating circuit”, “a multidimensional Fourier coefficient data output circuit” as appropriate. However, the specification fails to provide sufficient disclosure of the plurality of circuits to perform the claimed functions. Page 25 of the filed specification describes the term “unit” sed in the above described embodiments means software or a hardware component, such as FPGA or ASIC, but such recitation at most merely describes the term “unit”, and figures 6-8 illustrates flowcharts showing a fast multidimensional partial fourier transform method, but does not describe each substep is performed by a circuit as recited in the claims. Accordingly, the claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2, 4, 6, and 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 23-24, 26; claim 8 line 20-21, 23; and claim 9 line 24-25 and 27 recite terms “close to”, “ low-frequency” and “proximate to”, which are relative terms that render the claims indefinite. The term “close to”, “ low-frequency” and “proximate to”, is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Thus, the limitation of “the Fourier coefficient data are close to 0 except for a low-frequency portion proximate to a center of the Fourier map” is indefinite because it is unclear what constitutes as “close to”, “low frequency”, and “proximate to”.
Claim 1 lines 37, 40 recites “the input array”. It is unclear whether “the input array” is referring to an input array recited in claim 1 line 31 or an input array recited in claim 1 line 9. For examination purposes, Examiner interprets the input array as an input array recited in claim 1 line 31. Claims 8 line 32, 35 and claim 9 line 37, 41 recite similar limitations. Thus, they are also rejected for the same reasons.
Claim 1 line 37-38, 42 recites “the multidimensional partial Fourier transform”. It is unclear whether “the multidimensional partial Fourier transform” is referring to a multidimensional partial Fourier transform recited in claim 1 line 25 or a multidimensional partial Fourier transform recited in claim 1 line 32. For examination purposes, Examiner interprets the multidimensional partial Fourier transform as the multidimensional partial Fourier transform recited in claim 1 line 32. claim 9 line 37-38, 42 recite similar limitation. Thus, it is rejected for the same reasons.
Claim 1 line 53, 56, 59-60, 62, 67; claim 6 line 2-4 recites “the multidimensional Fourier coefficient data”. It is unclear whether “the multidimensional Fourier coefficient data” is referring to the multidimensional Fourier coefficient data recited in claim 1 line 18 or the one recited in claim 1 line 41-42. For examination purposes, Examiner interprets as the multidimensional Fourier coefficient data recited in claim 1 line 41-42.
Claim 8 line 48, 51, 54, 57, 59, 62 recites “the multidimensional Fourier coefficient data”. It is unclear whether “the multidimensional Fourier coefficient data” is referring to the multidimensional Fourier coefficient data recited in claim 8 line 24 or the one recited in claim 8 line 36-37. For examination purposes, Examiner interprets as the multidimensional Fourier coefficient data recited in claim 8 line 36-37.
Claim 9 line 53, 56, 59-60, 62, 67, recites “the multidimensional Fourier coefficient data”. It is unclear whether “the multidimensional Fourier coefficient data” is referring to the multidimensional Fourier coefficient data recited in claim 9 line 19 or the one recited in claim 9 line 42. For examination purposes, Examiner interprets as the multidimensional Fourier coefficient data recited in claim 9 line 42.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
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