Detailed Action
Status of Claims
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claims 1-20 are rejected.
This Action is Non-Final.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/30/2024,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir.1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a non-statutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
6. Claim 1 is non-provisionally rejected on the ground of non-statutory obviousness- type double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,158,850.
Application No: 18/932,094
Patent No: 12,158,850
Claim 1: A control device comprising:
a reporting device;
a buffer circuit; and
a processor comprising a core, a timer peripheral, and a peripheral direct memory access controller;
wherein the core is configured to configure the timer peripheral and the peripheral direct memory access controller to control an output port of the buffer circuit according to a communication scheme defined by the reporting device.
Claim 1: A controller device comprising:
a reporting device comprising a communication port;
a processor comprising a core, a timer peripheral, a peripheral direct memory access controller, and a receive port coupled to the communication port of the reporting device via a communication line, the timer peripheral configured to generate an enable signal and a timing signal; and
a buffer circuit comprising an enable port configured to receive the enable signal from the timer peripheral for enabling and disabling the buffer circuit, the buffer circuit further comprising an input port configured to receive the timing signal from the timer peripheral and an output port coupled to the communication line;
wherein the processor and the reporting device are configured to generate a communication signal on the communication line, wherein the processor is configured to: enable the buffer circuit and control the timing signal to cause the buffer circuit to generate an interrupt symbol during a timing period in the communication signal on the communication line; and
disable the buffer circuit to allow the reporting device to transmit at least one data bit on the communication line in a bit period immediately following the interrupt symbol; and
wherein the peripheral direct memory access controller of the processor is configured to store the at least one data bit received via the receive port in a receive buffer during the bit period; and
wherein the core of the processor is configured to subsequently retrieve the at least one data bit from the receiver buffer.
7. Claims 1-20 are provisionally rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,158,850 (Please note that as both the Patent and co-pending application claimed similar subject matters, and in the interest of time, the examiner is selecting the independent claim 1 from the Patent and claim 1 from co-pending application for the instant double patenting rejection).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shiotani (US Patent Application Pub. No: 20150071281 A1) in view of KUBO et al.(US Patent Application Pub. No: 20160062342 A1)
As per claim 1,Shiotani teaches a control device [Figs.1&2, a wireless transmitter 10A], comprising:
a reporting device [Figs.1&2, communication circuit 103.];
a buffer circuit [Figs.1& 2, a buffer memory row 124.]; and
a processor comprising a core [Figs.1&2,the CPU 104], a timer peripheral [Figs.1&2, timer 115.], and a peripheral direct memory access controller [Figs.1&2, DMA controller (DMAC) 105.].
Shiotani does not explicitly disclose wherein the core is configured to configure the timer peripheral and the peripheral direct memory access controller to control an output port of the buffer circuit according to a communication scheme defined by the reporting device.
KUBO discloses wherein the core is configured to configure the timer peripheral and the peripheral direct memory access controller to control an output port of the buffer circuit according to a communication scheme defined by the reporting device [Paragraph 0016, The I/O control unit may include a timer that may be referred to from the arithmetic processing unit and may be configured to output the control information to the I/O interface with a time resolution shorter than a control cycle for communication through the communication lines.].
It would have been obvious one ordinary skill in the art before the effective filling date of the claimed invention, to include KUBO’s an IO control system for controlling a machine into Shiotani’s wireless communication system for the benefit of a system synchronized with motor drive parts increases control efficiency of sensor information
obtained by a peripheral device without loading a processor of a numerical control unit, and outputs information to the peripheral device with high accuracy (KUBO, [0009]) to obtain the invention as specified in claim 1.
As per claim 2, Shiotani and KUBO teach all the limitations of claim 1 above, where Shiotani teaches, a control device, wherein the peripheral direct memory access controller is configured to store data bits received from the reporting device during a sampling period in a receive buffer of the processor [Shiotani, Paragraphs 0011-0012, The wireless transmitter and the wireless receiver communicate with each other in synchronization with a predetermined series of time slots, and the series of time slots includes a PCR time slot allotted to a predetermined number of time slots for transferring a PCR value from the wireless transmitter to the wireless receiver.]; and
wherein, after the sampling period, the peripheral direct memory access controller is configured to transfer the data bits from the receive buffer to a random-access memory (RAM) of the processor, and the core is configured to read the data bits from the RAM [Shiotani, Paragraphs 0011-0012; 0030, The wireless communication circuit 103 includes the scheduler circuit 121, a configuration register 122, a beacon generator 123, a buffer memory row 124, a MAC layer circuit 125, and a PRY layer circuit 126. When a time slot that the wireless transmitter 10A reserves for transmission comes, the scheduler circuit 121 starts transferring the TS packet stored in the RAM 106 to the buffer memory row 124 using DMA transfer.].
As per claim 3, Shiotani and KUBO teach all the limitations of claim 2 above, where Shiotani teaches, a control device, wherein the core is configured to retrieve the at least one data bit from the receiver buffer during times when the core is not performing critical tasks or controlling or communication with other devices [Shiotani, Paragraphs 0011-0012; 0030, The wireless communication circuit 103 includes the scheduler circuit 121, a configuration register 122, a beacon generator 123, a buffer memory row 124, a MAC layer circuit 125, and a PRY layer circuit 126. When a time slot that the wireless transmitter 10A reserves for transmission comes, the scheduler circuit 121 starts transferring the TS packet stored in the RAM 106 to the buffer memory row 124 using DMA transfer.].
As per claim 4, Shiotani and KUBO teach all the limitations of claim 1 above, where KUBO teaches, a control device, wherein the communication scheme defines a plurality of communication cycle periods, wherein each communication cycle period comprises a start period, a data period, a stop period, and an idle period [KUBO, Paragraphs 0005;0008, Usually, however, there are differences in data transfer cycle, data transfer rate, and/or the like between the interface connected to the amplifiers and the interface connected to the peripheral device and thus a time lag associated with data transfer is caused. The time lag associated with the data transfer may be a factor that deteriorates control accuracy for the peripheral device.].
As per claim 5, Shiotani and KUBO teach all the limitations of claim 4 above, where KUBO teaches, a control device, wherein each data cycle comprises a plurality of sampling periods with each sampling period having a timing period before a bit period, and wherein the reporting device is configured to communicate one or more data bits to the peripheral direct memory access controller of the processor during each bit period [KUBO, Paragraphs 0005;0008, Usually, however, there are differences in data transfer cycle, data transfer rate, and/or the like between the interface connected to the amplifiers and the interface connected to the peripheral device and thus a time lag associated with data transfer is caused. The time lag associated with the data transfer may be a factor that deteriorates control accuracy for the peripheral device.].
As per claim 6, Shiotani and KUBO teach all the limitations of claim 4 above, where KUBO teaches, a control device, wherein the core is configured to retrieve the at least one data bit from the receiver buffer during the idle period [KUBO, Paragraphs 0005; 0008, Usually, however, there are differences in data transfer cycle, data transfer rate, and/or the like between the interface connected to the amplifiers and the interface connected to the peripheral device and thus a time lag associated with data transfer is caused. The time lag associated with the data transfer may be a factor that deteriorates control accuracy for the peripheral device.].
As per claim 7, Shiotani and KUBO teach all the limitations of claim 6 above, where KUBO teaches, a control device, wherein the peripheral direct memory access controller is configured to configure the timer peripheral to generate an enable signal for disabling the buffer circuit during the idle period [KUBO, Paragraphs 0005; 0008; 0016, The I/O control unit may include a timer that may be referred to from the arithmetic processing unit and may be configured to output the control information to the I/O interface with a time resolution shorter than a control cycle for communication through the communication lines.].
As per claim 8, Shiotani and KUBO teach all the limitations of claim 4 above, where KUBO teaches, a control device, wherein the core of the processor is configured to configure the peripheral direct memory access controller for initiating the start period, the data period, the stop period, and the idle period of the communication cycle periods during execution of the communication scheme [KUBO, Paragraphs 0005; 0008;0016, The I/O control unit may include a timer that may be referred to from the arithmetic processing unit and may be configured to output the control information to the I/O interface with a time resolution shorter than a control cycle for communication through the communication lines.].
As per claim 9, Shiotani and KUBO teach all the limitations of claim 8 above, where Shiotani and KUBO teach, a control device, wherein the core of the processor is configured to configure the peripheral direct memory access controller to reconfigure the timer peripheral at the beginning of the start period, the data period, the stop period [KUBO, Paragraphs 0005; 0008;0016, The I/O control unit may include a timer that may be referred to from the arithmetic processing unit and may be configured to output the control information to the I/O interface with a time resolution shorter than a control cycle for communication through the communication lines.], and the idle period of the communication cycle periods and to store the at least one data bit in the receive buffer [Shiotani, Paragraphs 0011-0012; 0030, The wireless communication circuit 103 includes the scheduler circuit 121, a configuration register 122, a beacon generator 123, a buffer memory row 124, a MAC layer circuit 125, and a PRY layer circuit 126.].
As per claim 10, Shiotani and KUBO teach all the limitations of claim 4 above, where KUBO teaches, a control device, wherein the peripheral direct memory access controller is configured to configure the timer peripheral to generate a timing signal and an enable signal for producing a start symbol during the start period [KUBO, Paragraphs 0005;0008, Usually, however, there are differences in data transfer cycle, data transfer rate, and/or the like between the interface connected to the amplifiers and the interface connected to the peripheral device and thus a time lag associated with data transfer is caused. The time lag associated with the data transfer may be a factor that deteriorates control accuracy for the peripheral device.].
As per claim 11, Shiotani and KUBO teach all the limitations of claim 4 above, where KUBO teaches, a control device, wherein the timer peripheral is configured to drive an enable signal and a timing signal high to generate the start symbol, wherein the start symbol is defined by a longer time duration than the interrupt symbol [KUBO, Paragraphs 0005;0008, Usually, however, there are differences in data transfer cycle, data transfer rate, and/or the like between the interface connected to the amplifiers and the interface connected to the peripheral device and thus a time lag associated with data transfer is caused. The time lag associated with the data transfer may be a factor that deteriorates control accuracy for the peripheral device.].
As per claim 12, Shiotani and KUBO teach all the limitations of claim 1 above, where Shiotani teaches, a control device, wherein the communication scheme defines a timing of a transmission of the at least one data bit from the reporting device to the processor along the communication line [Shiotani, Paragraphs 0011-0012, The wireless transmitter and the wireless receiver communicate with each other in synchronization with a predetermined series of time slots, and the series of time slots includes a PCR time slot allotted to a predetermined number of time slots for transferring a PCR value from the wireless transmitter to the wireless receiver.].
As per claim 13, Shiotani and KUBO teach all the limitations of claim 12 above, where Shiotani teaches, a control device, wherein the processor comprises a receive port coupled to the communication port of the reporting device via the communication line [Shiotani, Paragraphs 0011-0012; 0030, The wireless communication circuit 103 includes the scheduler circuit 121, a configuration register 122, a beacon generator 123, a buffer memory row 124, a MAC layer circuit 125, and a PRY layer circuit 126. When a time slot that the wireless transmitter 10A reserves for transmission comes, the scheduler circuit 121 starts transferring the TS packet stored in the RAM 106 to the buffer memory row 124 using DMA transfer.].
As per claim 14, Shiotani and KUBO teach all the limitations of claim 1 above, where Shiotani teaches, a control device, wherein the buffer circuit comprises an enable port configured to receive an enable signal from the timer peripheral for enabling and disabling the buffer circuit [Shiotani, Paragraphs 0011-0012; 0030, The buffer memory row 124 includes multiple buffer memories as a queue for transferring data, and it is possible to configure priority of transfer for each buffer memory based on the priority stored in the configuration register 122. After performing MAC layer processes such as adding a header to the TS packet read from the buffer memory row 124, the MAC layer circuit 125 transfers the processed TS packet to the PHY layer circuit 126.].
As per claim 15, Shiotani and KUBO teach all the limitations of claim 1 above, where Shiotani teaches, a control device, wherein the buffer circuit comprises an input port configured to receive a timing signal from the timer peripheral and an output port coupled to a communication line, wherein the processor and the reporting device are configured to generate a communication signal on the communication line [Shiotani, Paragraphs 0011-0012; 0030, The wireless communication circuit 103 includes the scheduler circuit 121, a configuration register 122, a beacon generator 123, a buffer memory row 124, a MAC layer circuit 125, and a PRY layer circuit 126. When a time slot that the wireless transmitter 10A reserves for transmission comes, the scheduler circuit 121 starts transferring the TS packet stored in the RAM 106 to the buffer memory row 124 using DMA transfer.].
As per claim 16, Shiotani and KUBO teach all the limitations of claim 15 above, where Shiotani teaches, a control device, wherein the processor is configured to: enable the buffer circuit and control a timing signal to cause the buffer circuit to generate an interrupt symbol during a timing period in the communication signal on the communication line [Shiotani, Paragraphs 0011-0012; 0030, The wireless communication circuit 103 includes the scheduler circuit 121, a configuration register 122, a beacon generator 123, a buffer memory row 124, a MAC layer circuit 125, and a PRY layer circuit 126. When a time slot that the wireless transmitter 10A reserves for transmission comes, the scheduler circuit 121 starts transferring the TS packet stored in the RAM 106 to the buffer memory row 124 using DMA transfer.].
As per claim 17, Shiotani and KUBO teach all the limitations of claim 16 above, where KUBO teaches, a control device, wherein the processor is configured to: disable the buffer circuit to allow the reporting device to transmit at least one data bit on the communication line in a bit period immediately following the interrupt symbol [KUBO, Paragraphs 0005;0008; 0055,Thus increase in a load on processing in the motor control processor 12 is curbed. The output (control information for the control over the peripheral device) can be controlled with a time resolution finer than a communication cycle of the communication lines 20 by interrupt processing with use of the timer 42 provided inside the processor 34.].
As per claim 18, Shiotani and KUBO teach all the limitations of claim 17 above, where KUBO teaches, a control device, wherein the peripheral direct memory access controller of the processor is configured to store the at least one data bit received via the receive port in a receive buffer during the bit period [KUBO, Paragraphs 0005; 0008; 0055,Thus increase in a load on processing in the motor control processor 12 is curbed. The output (control information for the control over the peripheral device) can be controlled with a time resolution finer than a communication cycle of the communication lines 20 by interrupt processing with use of the timer 42 provided inside the processor 34.].
As per claim 19, Shiotani and KUBO teach all the limitations of claim 18 above, where KUBO teaches, a control device, wherein the core of the processor is configured to retrieve the at least one data bit from the receiver buffer [KUBO, Paragraphs 0005; 0008; 0055,Thus increase in a load on processing in the motor control processor 12 is curbed. The output (control information for the control over the peripheral device) can be controlled with a time resolution finer than a communication cycle of the communication lines 20 by interrupt processing with use of the timer 42 provided inside the processor 34.].
As per claim 20, Shiotani and KUBO teach all the limitations of claim 19 above, where KUBO teaches, a control device, wherein the core is configured to retrieve the at least one data bit from the receiver buffer independent of any interaction of the timer peripheral and the peripheral direct memory access controller with the reporting device [KUBO, Paragraphs 0005; 0008; 0055,Thus increase in a load on processing in the motor control processor 12 is curbed. The output (control information for the control over the peripheral device) can be controlled with a time resolution finer than a communication cycle of the communication lines 20 by interrupt processing with use of the timer 42 provided inside the processor 34.].
Conclusion
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
References Considered Pertinent but not relied upon
Jenkins et al. (US Patent Application Pub. No: 20030202530 A1) teaches a circular segmented bus such as data bus and address bus connected to each core such as processor, peripheral device in the integrated circuit, transfers data between the cores and an arbiter arbitrates the core that transmits data at any time.
Reinig et al. (US Patent Application Pub. No: 20180165240 A1) teaches a network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second device, wherein the first device is configured in accordance with a first bus interconnect protocol and the second device is configured in accordance with a second bus interconnect protocol; a second buffer configured to buffer a second flow of a second type of commands from the first device to the second device; and an arbiter configured to arbitrate between the first flow and the second flow, and selectively output one or more commands of the first type and one or more commands of the second type.
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/GETENTE A YIMER/Primary Examiner, Art Unit 2181