DETAILED ACTION
Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/10/2025 have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hudson et al. (US Patent Publication No. 2017/0124935; hereinafter Hudson).
With reference to claims 1, 14, and 18, Hudson discloses a display system (100), method, and non-transitory computer-readable medium storing instructions that, when executed, cause a frame controller of the display system (100) to perform a process (see paragraph 22) comprising:
an array of pixels (105) (see paragraphs 67-68, 71, 76; Figs. 1, 4); and
a frame controller configured to cause the array of pixels to display an image frame by performing a series of successive field updates (see paragraph 79; Fig. 5A), the series of successive field updates including:
a first field update in which a first write pointer circuit tracks a first traversal (in teaching first write pointer (280); see paragraphs 76-77, 93; Figs. 4, 7-8), during a first update period, across the array of pixels to update the array of pixels from a first image field of an image field sequence to a second image field of the image field sequence (in teaching odd sequence of rows 1-N; see paragraphs 77-79, 91-93; Figs. 4-8), and
a second field update in which a second write pointer circuit tracks a second traversal (in teaching second write pointer (282); see paragraphs 76-77, 93; Figs. 4, 7-8), during a second update period, across the array of pixels to update the array of pixels from the second image field to a third image field of the image field sequence (in teaching even sequence of rows 1-N; see paragraphs 77-79, 91-93; Figs. 4-8);
wherein the second update period (282) of the second field update overlaps (288) the first update period (280) of the first field update (see paragraphs 93, 99; Figs. 7-8).
With reference to claim 2, Hudson discloses the display system of claim 1, and further discloses wherein: a minimum panel update period is defined as a time period in which the frame controller uses a single write pointer circuit to track traversal across the array of pixels to update the array of pixels (see paragraphs 76-77, 81-89; Figs. 4-8); the first update period and the second update period are each at least twice the minimum panel update period (see paragraph 93; Figs. 4-8); the second image field is displayed for a second field duration shorter than the minimum panel update period (see paragraph 93; Figs. 4-8); and the third image field is displayed for a third field duration longer than the minimum panel update period, such that a sum of the second field duration and the third field duration is at least twice the minimum panel update period (in teaching having multiple write pointers active at the same time; see paragraphs 98-101; Figs. 7-8).
With reference to claims 3, 15, and 19, Hudson discloses the display system of claim 1, 14, or 18, and further discloses wherein: a minimum panel update period is defined as a time period in which the frame controller of the display system uses a single write pointer circuit to track traversal across the array of pixels to update the array of pixels (see paragraphs 76-77; Figs. 4A-B); the series of successive field updates further includes a third field update in which a third write pointer circuit tracks a third traversal, during a third update period, across the array of pixels to update the array of pixels from the third image field to a fourth image field of the image field sequence (see paragraphs 98-100; Figs. 8A-B); the first update period, the second update period, and the third update period are each at least three times the minimum panel update period (in teaching having multiple write pointers active at the same time; see paragraphs 98-101; Figs. 7-8); the second image field is displayed for a second field duration shorter than the minimum panel update period; the third image field is displayed for a third field duration shorter than the minimum panel update period; and the fourth image field is displayed for a fourth field duration longer than the minimum panel update period, such that a sum of the second field duration, the third field duration, and the fourth field duration is at least three times the minimum panel update period (see paragraphs 101-102, 104-105; Figs. 8A-B).
With reference to claim 4, Hudson discloses the display system of claim 1, and further discloses wherein the series of successive field updates is performed such that each image field of the image field sequence is displayed for a unique field duration distinct from other field durations of other image fields of the image field sequence (see paragraph 106; Fig. 9).
With reference to claim 5, Hudson discloses the display system of claim 1, and further discloses wherein the first image field of the image field sequence includes an array of binary values corresponding to the array of pixels (see paragraphs 10-11; 79; Figs. 5).
With reference to claim 6, Hudson discloses the display system of claim 1, and further discloses wherein the first image field of the image field sequence includes an array of multi-bit values corresponding to the array of pixels (see paragraphs 10-11).
With reference to claim 7 and 16, Hudson discloses the display system of claim 1 or 14, and further discloses wherein: the image frame is displayed by using a binary pulse-width modulation (PWM) technique to apply, to the array of pixels (see paragraphs 10-11), an array of multi-bit brightness values that corresponds to the array of pixels for the image frame (see paragraphs 10-11); the first image field of the image field sequence includes a first array of binary values forming a first bit plane of the array of multi-bit brightness values (see paragraphs 111-112; Figs. 6-8, 14-17); and the second image field of the image field sequence includes a second array of binary values forming a second bit plane of the array of multi-bit brightness values (see paragraphs 111-112; Figs. 6-8, 14-17).
With reference to claim 8, Hudson discloses the display system of claim 1, and further discloses wherein: the array of pixels is arranged in a plurality of rows on a display panel (see paragraph 66); and the first traversal and the second traversal across the array of pixels are each performed in a sequential update order that begins with a top row of the plurality of rows and continues sequentially through successive rows until reaching a bottom row of the plurality of rows (see paragraphs 76-77; Figs. 4-8).
With reference to claim 9, Hudson discloses the display system of claim 1, and further discloses wherein: the array of pixels is arranged in a plurality of rows on a display panel (see paragraph 66); and the first traversal and the second traversal across the array of pixels are each performed in a nonsequential update order distinct from a sequential update order that begins with a top row of the plurality of rows and continues sequentially through successive rows until reaching a bottom row of the plurality of rows (see paragraph 26, 93-95; Figs. 7-8).
With reference to claim 10, Hudson discloses the display system of claim 1, and further discloses wherein: the array of pixels is arranged on a display panel with respect to a plurality of display units (28, 32, 36); during the first field update, the first write pointer circuit tracks the plurality of display units, beginning with a first display unit, to update each of the plurality of display units; and the second update period of the second field update begins immediately subsequent to the first display unit being updated (see paragraphs 73-74).
With reference to claim 11, Hudson discloses the display system of claim 10, and further discloses wherein the plurality of display units are implemented as single rows on the display panel (see paragraphs 77, 81, 89).
With reference to claim 12, Hudson discloses the display system of claim 10, and further discloses wherein the plurality of display units are implemented as multi-row groups on the display panel (see paragraphs 91, 104; Figs. 4-8).
With reference to claim 13, Hudson discloses the display system of claim 10, and further discloses wherein the plurality of display units are implemented as partial rows on the display panel (see paragraphs 93, 100).
With reference to claim 17 and 20, Hudson discloses method of claim 14 or 18, and further discloses wherein: the array of pixels is arranged on a display panel with respect to a plurality of display units implemented by one of: single rows on the display panel, multi-row groups on the display panel, or partial rows on the display panel (see paragraphs 77, 81, 89, 91, 93, 100, 104); during the first field update, the first write pointer circuit tracks the plurality of display units, beginning with a first display unit, to update each of the plurality of display units; and the second update period of the second field update begins immediately subsequent to the first display unit being updated (see paragraphs 73-74).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LO et al. (US2016/0077367) discloses a method of PWM which preform addressing display pixels with the usage of a first write pointer and a second write pointer (see paragraphs 134-172; Figs. 9-13).
Conclusion
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/ADE/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625