DETAILED ACTION
Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hudson et al. (US Patent Publication No. 2017/0124935; hereinafter Hudson) in view of Guo et al. (US Patent Publication No. 2022/0036841; hereinafter Guo).
With reference to claims 1, 14, and 18, Hudson discloses a display system (100), method, and non-transitory computer-readable medium storing instructions that, when executed, cause a frame controller of the display system (100) to perform a process (see paragraph 22) comprising:
an array of pixels (105) arranged on a display panel with respect to display units (see paragraphs 67-68, 71, 76; Figs. 1, 4); and
a frame controller configured to cause the array of pixels to display an image frame by performing a series of successive field updates (see paragraph 79; Fig. 5A), the series of successive field updates including:
a first update in which a first circuit tracks a first traversal (in teaching first write pointer (280); see paragraphs 76-77, 93; Figs. 4, 7-8), during a first period, across the array of pixels to update the array of pixels from a first subframe to a second subframe of a sequence (in teaching odd sequence of rows 1-N; see paragraphs 77-79, 91-93; Figs. 4-8), and
a second update in which a second circuit tracks a second traversal (in teaching second write pointer (282); see paragraphs 76-77, 93; Figs. 4, 7-8), during a second period overlapping the first period, across the array of pixels to update the array of pixels from the second subframe to a third subframe of the sequence (in teaching even sequence of rows 1-N; see paragraphs 77-79, 91-93; Figs. 4-8);
wherein the first update tracked by the first circuit includes updating the display units in a update order and the second update tracked by the second circuit is interleaved with the first update and further updates the display units in the update order (see paragraphs 93, 99; Figs. 7-8).
While disclosing updating the display, wherein it may be possible to vary the write order (see paragraph 123), Hudson fails to specifically disclose a random or quasi random update order as recited.
Guo discloses a driving method for a display device wherein the controller is configured to cause the array of pixels to display an image frame by performing a series of updates, including updating the display units in a random or quasi random update order (in teaching sequential or non-sequential driving; see paragraph 18).
Therefore it would have been obvious to one of ordinary skill in the art to allow the usage of a random or quasi random write order similar to that which is taught by Guo to be carried out in a system similar to that which is taught by Hutson to thereby improve display quality
With reference to claim 2, Hudson and Guo disclose method of claim 1, wherein Hudson further discloses wherein: a minimum panel update period is defined as a time period in which the frame controller uses a single circuit to track traversal across the array of pixels to update the array of pixels (see paragraphs 76-77, 81-89; Figs. 4-8); the first period and the second period are each at least twice the minimum panel update period (see paragraph 93; Figs. 4-8); the second subframe is displayed for a second duration shorter than the minimum panel update period (see paragraph 93; Figs. 4-8); and the third subframe is displayed for a third duration longer than the minimum panel update period, such that a sum of the second duration and the third duration is at least twice the minimum panel update period (in teaching having multiple write pointers active at the same time; see paragraphs 98-101; Figs. 7-8).
With reference to claims 3, 15, and 19, Hudson and Guo disclose method of claim 1, 14, or 18, wherein Hudson further discloses wherein: a minimum panel update period is defined as a time period in which the frame controller of the display system uses a single circuit to track traversal across the array of pixels to update the array of pixels (see paragraphs 76-77; Figs. 4A-B); the series of successive field updates further includes a third update in which a third circuit tracks a third traversal, during a third period, across the array of pixels to update the array of pixels from the third subframe to a fourth subframe of the image field sequence (see paragraphs 98-100; Figs. 8A-B); the first period, the second period, and the third period are each at least three times the minimum panel update period (in teaching having multiple write pointers active at the same time; see paragraphs 98-101; Figs. 7-8); the second subframe is displayed for a second duration shorter than the minimum panel update period; the third subframe is displayed for a third duration shorter than the minimum panel update period; and the fourth subframe is displayed for a fourth duration longer than the minimum panel update period, such that a sum of the second duration, the third duration, and the fourth duration is at least three times the minimum panel update period (see paragraphs 101-102, 104-105; Figs. 8A-B).
With reference to claim 4, Hudson and Guo disclose method of claim 1, wherein Hudson further discloses wherein the series of successive field updates is performed such that each subframe of the sequence is displayed for a unique duration distinct from other durations of other subframes of the sequence (see paragraph 106; Fig. 9).
With reference to claim 5, Hudson and Guo disclose method of claim 1, wherein Hudson further discloses wherein the first subframe of the sequence includes an array of binary values corresponding to the array of pixels (see paragraphs 10-11; 79; Figs. 5).
With reference to claim 6, Hudson and Guo disclose method of claim 1, wherein Hudson further discloses wherein the first subframe of the image field sequence includes an array of multi-bit values corresponding to the array of pixels (see paragraphs 10-11).
With reference to claim 7 and 16, Hudson and Guo disclose method of claim 1 and 14, wherein Hudson further discloses wherein: the image frame is displayed by using a binary pulse-width modulation (PWM) technique to apply, to the array of pixels (see paragraphs 10-11), an array of multi-bit brightness values that corresponds to the array of pixels for the image frame (see paragraphs 10-11); the first subframe of the sequence includes a first array of binary values forming a first bit plane of the array of multi-bit brightness values (see paragraphs 111-112; Figs. 6-8, 14-17); and the second subframe of the sequence includes a second array of binary values forming a second bit plane of the array of multi-bit brightness values (see paragraphs 111-112; Figs. 6-8, 14-17).
With reference to claim 10, Hudson and Guo disclose method of claim 1, wherein Hudson further discloses wherein: the first update, begins updating display units with a first display unit; and the second update interleaved with the first update begins immediately subsequent to the first display unit being updated (see paragraphs 73-74; Figs. 7-8).
With reference to claim 11, Hudson and Guo disclose method of claim 10, wherein Hudson further discloses wherein the display units are implemented as single rows on the display panel (see paragraphs 77, 81, 89).
With reference to claim 12, Hudson and Guo disclose method of claim 10, wherein Hudson further discloses wherein the display units are implemented as multi-row groups on the display panel (see paragraphs 91, 104; Figs. 4-8).
With reference to claim 13, Hudson and Guo disclose method of claim 10, wherein Hudson further discloses wherein the display units are implemented as partial rows on the display panel (see paragraphs 93, 100).
With reference to claims 17 and 20, Hudson and Guo disclose method of claim 14 or 18, wherein Hudson further discloses wherein: during the first update, begins updating the display units, with a first display unit; and the second update interleaved with the first update begins immediately subsequent to the first display unit being updated (see paragraphs 73-74).
With reference to claim 21, Hudson and Guo disclose method of claim 7, wherein Guo further discloses wherein the display units are implements as multi-row groups on the display panel (100) (see paragraphs 18, 39; Figs. 1-4).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hudson in view of Guo as applied to claim 1 above, and further in view of Tanaka et al. (US Patent Publication No. 2009/0015591; hereinafter Tanaka).
While disclosing all that is required as explained above, however fails to disclose partial rows as recited.
Tanaka discloses an image generating apparatus which allows the
display units to be implemented as partial rows on the display panel (see paragraph 9).
Therefore it would have been obvious to one of ordinary skill in the art to allow partial row writes similar to that which is taught by Tanaka to be carried out in a system similar to that which is taught by Hudson and Guo to thereby reduce power consumption and write times (see Tanaka; paragraphs 12-13).
Response to Arguments
Applicant’s arguments with respect to claims 1-7 and 10-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LO et al. (US2016/0077367) discloses a method of PWM which preform addressing display pixels with the usage of a first write pointer and a second write pointer (see paragraphs 134-172; Figs. 9-13).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ADE/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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