DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim status
Claims 1-20 are pending; claims 1 and 16 are independent.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Objections
Claims 16 and 18 are objected to because of the following informalities:
Claim 16, recited “a plurality of first reference electrode line”, line 4, should be change to “a plurality of first reference electrode lines”; and
Claim 18, recited “…tothe first voltage” , line 4, should be “…to the first voltage”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa (US 2014/0240301), and further in view of Hsu (US 2018/0012556).
Regarding claim 1, Yamakawa teaches a panel driving device (fig. 2), comprising:
a panel (fig. 2, a display unit 400), comprising:
a data line, configured to transmit a data signal (figs 2, 3, Paras 0054 and 0057-0058, wherein the source driver 300 applies driving video signals to the source bus lines);
a reference electrode line, configured to transmit a reference signal (fig. 3 and para 0054, wherein a common electrode 42 which is a counter electrode for providing a common voltage to the plurality of pixel formation portions); and
a first pixel, configured to receive the data signal and the reference signal (fig. 3 and Para 0054, wherein each pixel formation portion is connected to a source bus line SL and a common electrode 42 which is a counter electrode for providing a common voltage to the plurality of pixel formation portions);
wherein the first pixel is configured to generate a pixel signal according to the data signal and the reference signal (fig. 3 and para 0054, wherein each pixel formation portion includes a thin film transistor (TFT) 40 which is a switching element connected at its gate terminal to a gate bus line GL passing through a corresponding intersection, and connected at its source terminal to a source bus line SL passing through the intersection; a pixel electrode 41 connected to the drain terminal of the thin film transistor 40; a common electrode 42 which is a counter electrode for providing a common voltage to the plurality of pixel formation portions);
wherein during a positive frame period, a difference between a first voltage value of the pixel signal and a first reference voltage value of the reference signal is a first driving voltage value (see reproduced fig. 1 below, frame period from t2 to t3 and Paras 0067-0068);
wherein during a negative frame period, a difference between a second voltage value of the pixel signal and a
wherein during a charging period which is between the negative frame period and the positive frame period, the pixel signal comprises a third voltage value which is greater than the second voltage value and is less than or equal to the first voltage value (see reproduced fig. 1 below, frame period from t3 to t5 and Para 0069).
Yamakawa does not expressly disclose an absolute value of the first driving voltage value is about the same as an absolute value of the second driving voltage value.
However, Hsu discloses “an absolute value of the first driving voltage value is about the same as an absolute value of the second driving voltage value”, see fig. 6 and Para 0035.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a device of Yamakawa with teaching of Hsu to include an absolute value of a difference between the positive data voltage V1′ and the second common voltage VCOM2 is the same as an absolute value of a difference between the negative data voltage V2′ and the second common voltage VCOM2, as a known technique to yield a predictable result.
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Regarding claim 2, Yamakawa in view of Hsu teaches the panel driving device of claim 1, wherein during an initial period before the positive frame period, the pixel signal comprises a fourth voltage value which is greater than the third voltage value and is less than or equal to the first voltage value (see reproduced fig. 1 above, a period from t0 to t3=2 and Paras 0067-0068, Yamakawa).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa (US 2014/0240301), in view of Cheng (US 2020/0302882) and further in view of Hsu (US 2018/0012556).
Regarding claim 16, Yamakawa teaches a panel driving device (fig. 2), comprising:
a panel (fig. 2, a display unit 400), comprising:
a data line, configured to transmit a data signal (figs 2, 3, Paras 0054 and 0057-0058, wherein the source driver 300 applies driving video signals to the source bus lines);
a
a first pixel, configured to receive the data signal and the reference signa l(fig. 3 and Para 0054, wherein each pixel formation portion is connected to a source bus line SL and a common electrode 42 which is a counter electrode for providing a common voltage to the plurality of pixel formation portions);
wherein the first pixel is configured to generate a pixel signal according to the data signal and the reference signal (fig. 3 and para 0054, wherein each pixel formation portion includes a thin film transistor (TFT) 40 which is a switching element connected at its gate terminal to a gate bus line GL passing through a corresponding intersection, and connected at its source terminal to a source bus line SL passing through the intersection; a pixel electrode 41 connected to the drain terminal of the thin film transistor 40; a common electrode 42 which is a counter electrode for providing a common voltage to the plurality of pixel formation portions);
wherein during a positive frame period, a difference between a first voltage value of the pixel signal and a first reference voltage value of the reference signal is a first driving voltage value (see reproduced fig. 1 above in claim 1, frame period from t2 to t3 and Paras 0067-0068);
wherein during a negative frame period, a difference between a second voltage value of the pixel signal and a
wherein during a charging period which is between the negative frame period and the positive frame period, the pixel signal comprises a third voltage value which is greater than the second voltage value and is less than or equal to the first voltage value(see reproduced fig. 1 above in claim 1, frame period from t3 to t5 and Para 0069).
Yamakawa does not expressly disclose a plurality of first reference electrode line.
However, Cheng disclose a plurality of first reference electrode line, see fig. 1 and Para 0019.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a device of Yamakawa with teaching of Cheng to include a plurality of common voltage lines, as a known technique to yield a predictable result.
Yamakawa in view of Cheng does not expressly disclose a second reference electrode line, overlapping and coupled to each of the first reference electrode lines; and an absolute value of the first driving voltage value is about the same as an absolute value of the second driving voltage value.
However, Hsu discloses “a second reference electrode line, overlapping and coupled to each of the first reference electrode lines, see fig. 2 and para 0028; and an absolute value of the first driving voltage value is about the same as an absolute value of the second driving voltage value”, see fig. 6 and Para 0035.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a device of Yamakawa in view of Cheng with teaching of Hsu to include an absolute value of a difference between the positive data voltage V1′ and the second common voltage VCOM2 is the same as an absolute value of a difference between the negative data voltage V2′ and the second common voltage VCOM2, as a known technique to yield a predictable result.
Regarding claim 17, Yamakawa in view of Cheng and in view of Hsu teaches the panel driving device of claim 16, wherein during a first period, the data signal comprises a first data voltage value, the reference signal comprises the first reference voltage value, and the pixel signal comprises an initial voltage value, wherein the first period is located before the positive frame period (see reproduced fig. 1 above, a period from t0 to t3=2 and Paras 0067-0068, Yamakawa).
Allowable Subject Matter
Claims 3-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Iwamoto (US 2019/0108781), relates to a display device including: a plurality of source lines extending in a first direction; and a plurality of gate lines extending in a second direction that intersects with the first direction. A plurality of switching elements are connected to one of the plurality of source lines. Each of the plurality of switching elements is connected to one of the plurality of gate lines. The plurality of switching elements connected to the source line are aligned in the first direction so as to be alternately located on one side and another side of the source line.
Lee (US 2010/0149158), relates to an electrophoresis display, more particularly, to an electrophoresis display that is able to reduce the size of circuits for driving a display panel by decreasing driving voltages required to display images and the unit cost of the product.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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/S.E.E/Examiner, Art Unit 2625 6/9/2026
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625
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