DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 13 – 28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 - 12 of Tsuchiya et al U.S. Patent No. 12,160,676 in view of Morimoto US Publication No. 2020/0244909.
Regarding claim 13 Tsuchiya et al discloses of applicant’s A photoelectric conversion device comprising: a photodiode configured to perform avalanche multiplication; a control circuit configured to control based on a first control signal including pulses that periodically repeat transitions from a first level to a second level; and a pixel signal processing circuit, the pixel signal processing circuit being enabled based on a second control signal, wherein after the pixel signal processing circuit is disabled based on the second control signal and before the pixel signal processing circuit is enabled based on the second control signal, the first control signal transitions from the first level to the second level and transitions from the second level to the first level (claim 1, A photoelectric conversion device comprising: a photodiode configured to perform avalanche multiplication; a recharging circuit, as a control circuit, configured to perform a recharging operation to bring the photodiode after the avalanche multiplication into a state in which the avalanche multiplication can be performed again based on a first control signal including pulses that periodically repeat transitions from a first level to a second level; and a counter, as a pixel signal processing circuit, configured to count the number of occurrences of the avalanche multiplication by being enabled based on a second control signal, wherein before the counter is enabled based on the second control signal, the first control signal transitions from the first level to the second level and transitions from the second level to the first level);
Tsuchiya et al discloses a recharge control circuit that performs a recharging operation of the photodiode and a counter signal processing circuit but does not expressively disclose a control circuit configured to control a voltage supplied to the photodiode; a pixel signal processing circuit to which a signal form the photodiode is input;
Morimoto teaches a pulse circuit that controls a photodiode and a counter that counts incidence photons on the photodiode. Morimoto teaches f Fig. 1 – 13B of applicant’s a control circuit configured to control a voltage supplied to the photodiode (paragraph 0040 at a time t3, the pulse generation circuit 13 changes the signal Pctrl to the low level. Accordingly, the PMOS transistor of the photodiode control circuit 14 is turned on, and recharging operation for returning the signal Vcath to the voltage VDD is performed. This period is a period in which the photodiode control circuit 14 is in a recharging state for returning the photodiode PD to the state where the avalanche multiplication is possible such that a pulse generation circuit 13 changes is a control circuit configured to control a VDD voltage supplied to the photodiode PD); a pixel signal processing circuit to which a signal form the photodiode is input (paragraph 0035 the counter 16 counts the number of times the signal Sig, which is output by the AND circuit 17, transitions from a low level to a high level. Accordingly, the counter 16 generates a count signal including a count value corresponding to incidence of a photon on the photodiode PD such that a pixel counter signal processing circuit to which a signal form the photodiode PD is input so as to count signal including a count value corresponding to incidence of a photon on the photodiode PD).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Tsuchiya et al in a manner similar to Tsuchiya et al. Doing so would result improving Tsuchiya et al invention in a similar way as Tsuchiya et al – namely the ability to provide a pulse circuit that controls a photodiode and a counter that counts incidence photons on the photodiode, in Tsuchiya et al invention, to the circuit with a recharge control circuit that performs a recharging operation of the photodiode and a counter signal processing circuit in Tsuchiya et al invention.
Regarding claim 14 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the control circuit is enabled further based on a third control signal (claim 2, wherein the recharging circuit performs the recharging operation further based on a third control signal for enabling the recharging operation).
Regarding claim 15 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein enabling of the control circuit based on the third control signal is performed before enabling of the pixel signal processing circuit based on the second control signal (claim 3, wherein the enabling of the recharging operation based on the third control signal is performed before the enabling of the counter based on the second control signal).
Regarding claim 16 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the pixel signal processing circuit includes a counter configured to count the number of occurrences of the avalanche multiplication, and wherein the counter is enabled based on the second control signal (claim 1, a counter configured to count the number of occurrences of the avalanche multiplication by being enabled based on a second control signal).
Regarding claim 17 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the control circuit includes a recharging circuit configured to perform a recharging operation to bring the photodiode after the avalanche multiplication into a state in which the avalanche multiplication can be performed again (claim 1, a recharging circuit configured to perform a recharging operation to bring the photodiode after the avalanche multiplication into a state in which the avalanche multiplication can be performed again based on a first control signal including pulses that periodically repeat transitions from a first level to a second level).
Regarding claim 18 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the recharging circuit performs the recharging operation further based on a third control signal for enabling the recharging operation (claim 2, wherein the recharging circuit performs the recharging operation further based on a third control signal for enabling the recharging operation).
Regarding claim 19 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the enabling of the recharging operation based on the third control signal is performed before the enabling of the counter based on the second control signal (claim 2, wherein the enabling of the recharging operation based on the third control signal is performed before the enabling of the counter based on the second control signal).
Regarding claim 20 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s further comprising a first logic circuit configured to output a signal for controlling on or off of the recharging operation of the recharging circuit based on the first control signal and the third control signal (claim 4, further comprising a first logic circuit configured to output a signal for controlling on or off of the recharging operation of the recharging circuit based on the first control signal and the third control signal).
Regarding claim 21 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s further comprising a second logic circuit configured to output a signal for changing a count value to the counter based on the second control signal and an output signal of the photodiode (claim 5, further comprising a second logic circuit configured to output a signal for changing a count value to the counter based on the second control signal and an output signal of the photodiode).
Regarding claim 22 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s further comprising a second logic circuit and a third logic circuit, wherein the third logic circuit outputs a fourth control signal to the second logic circuit based on the first control signal and the second control signal, and wherein the second logic circuit outputs a signal for changing a count value to the counter based on the fourth control signal and an output signal of the photodiode (claim 6, further comprising a second logic circuit and a third logic circuit, wherein the third logic circuit outputs a fourth control signal to the second logic circuit based on the first control signal and the second control signal, and wherein the second logic circuit outputs a signal for changing a count value to the counter based on the fourth control signal and an output signal of the photodiode).
Regarding claim 23 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the recharging circuit performs the recharging operation further based on a fifth control signal for resetting a count value of the counter (claim 7, wherein the recharging circuit performs the recharging operation further based on a fifth control signal for resetting a count value of the counter).
Regarding claim 24 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein the recharging circuit performs the recharging operation at a timing when the count value is reset (claim 8, wherein the recharging circuit performs the recharging operation at a timing when the count value is reset).
Regarding claim 25 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s further comprising a fourth logic circuit configured to output a signal for controlling on or off of the recharging operation of the recharging circuit based on the first control signal, a third control signal for enabling the recharging operation, and the fifth control signal (claim 9, further comprising a fourth logic circuit configured to output a signal for controlling on or off of the recharging operation of the recharging circuit based on the first control signal, a third control signal for enabling the recharging operation, and the fifth control signal).
Regarding claim 26 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s wherein a length of a period from when the recharging operation is performed to when the counter is enabled is equal to or less than a period of the pulses included in the first control signal (claim 10, wherein a length of a period from when the recharging operation is performed to when the counter is enabled is equal to or less than a period of the pulses included in the first control signal).
Regarding claim 27 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s A light detection system comprising: the photoelectric conversion device according to claim 13; and a signal processing unit configured to process a signal output from the photoelectric conversion device (claim 11, A light detection system comprising: the photoelectric conversion device according to claim 1; and a signal processing unit configured to process a signal output from the photoelectric conversion device).
Regarding claim 28 of the combination of Tsuchiya et al in view of Morimoto, Tsuchiya et al further discloses of applicant’s A movable body comprising: the photoelectric conversion device according to claim 13; a distance information acquisition unit configured to acquire distance information to an object from a signal output from the photoelectric conversion device; and a control unit configured to control the movable body based on the distance information (claim 12, A movable body comprising: the photoelectric conversion device according to claim 1; a distance information acquisition unit configured to acquire distance information to an object from a signal output from the photoelectric conversion device; and a control unit configured to control the movable body based on the distance information).
Conclusion
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/MARK T MONK/Primary Examiner, Art Unit 2637