DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed by Applicant on 04/02/2026. This action is made FINAL.
Examiner’s Notes
The Applicant newly mentions that the synchronization in the “second-mode,” the high scan rate mode causes the adjacent clocks to have the same phase to simultaneously scan two gate lines. However, it is not clear from the claim language whether the “first-mode,” the normal scan rate mode causes the synchronization of clocks to have a phase difference in a different manner. The pending claims do not differentiate the phase differences in different modes.
The underlined parts of the forthcoming action are the newly added parts addressing Applicant’s amendments.
Response to Arguments
Applicant’s arguments with respect to claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (Publication number: US 2019/0197964) in view of Baek et al (Publication number: US 2022/0208111) in view of Kim et al (Publication number: US 2020/0258463).
Consider Claim 1, Cho et al shows a gate driver (see figure 1; read as gate driver 200 in addition to level shifter IC 500), comprising:
(a) A level shifter configured to output first-mode gate clocks in a normal scan rate mode, and output second-mode gate clocks in a high scan rate mode (see figures 1 and 6; paragraphs 61-63); (Read as level shifter IC 500. The first buffer 504 and the second buffer 506 store the on clock and the off clock fed back from the MUX1 508 and the MUX2 510, respectively, during every horizontal period in the form of data and update the on clock and the off clock. Therefore, during the enable period of the PDRW control signal, the MUX1 508 and the MUX2 510 can repeatedly output the on clock and the off clock which are stored in the first buffer 504 and the second buffer 506, respectively, during every horizontal period).
(b) A gate shift register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode, and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode (see figures 1 and 6; paragraphs 61-63); (Read as level shifter IC 500. The first buffer 504 and the second buffer 506 store the on clock and the off clock fed back from the MUX1 508 and the MUX2 510, respectively, during every horizontal period in the form of data and update the on clock and the off clock. Therefore, during the enable period of the PDRW control signal, the MUX1 508 and the MUX2 510 can repeatedly output the on clock and the off clock which are stored in the first buffer 504 and the second buffer 506, respectively, during every horizontal period).
(c) Wherein adjacent gate clocks of the first-mode gate clocks have a phase difference equal to 1 horizontal period (see paragraphs 80-82; figure 3); (The difference is equal to units of 1H (1 horizontal period)).
(d) Wherein adjacent gate clock pairs of the second-mode gate clocks have a phase difference equal to 1 horizontal period, and two gate clocks of the same gate clock pair are synchronized with each other (see paragraph 83); (A receiver RX of the level shifter IC 500-3 receives the first and second serial timing information STD1 and STD2 received from the timing controller 400-3 in synchronization with the clock CLK).
However, Cho et al does not specifically show that the first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock.
In related art, Baek et al shows that the first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock (see paragraph 108); (the 16-phase level shifter 15 receives the first reference signal GCLK and the second reference signal MCLK as an input from the timing controller 10).
Therefore, it would have been obvious to a person of ordinary skill in the art to incorporate the level shifter of Baek et al into the gate driver of Cho et al in order to output 16 types of carry clock signals (see Baek et al; paragraph 108).
However, Cho et al, in view of Baek et do not specifically show that the two gate clocks of the same gate clock pair are synchronized with each other to have the same phase to simultaneously scan two gate lines.
In related art, Kim et al shows that the two gate clocks of the same gate clock pair are synchronized with each other to have the same phase to simultaneously scan two gate lines (see figures 5 and 8; also see paragraphs 43-45); (Figure 8 shows that CLK1 and CLK2 have the same phase).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Kim et al into the teaching of Cho et al and Baek et al in order to the gate lines can be scanned simultaneously (See Kim et al; paragraphs 43-45).
Consider Claim 9, Cho et al shows a display device (see figure 1), comprising:
(a) A display panel including a plurality of panels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels (see figure 1).
(b) A gate driver configured to drive the plurality of gate lines; and a data driver configured to drive the plurality of data lines, wherein the gate driver comprises: a level shifter configured to output first-mode gate clocks in a normal scan rate mode, and output second-mode gate clocks in a high scan rate mode (see figures 1 and 6; paragraphs 61-63); (Read as level shifter IC 500. The first buffer 504 and the second buffer 506 store the on clock and the off clock fed back from the MUX1 508 and the MUX2 510, respectively, during every horizontal period in the form of data and update the on clock and the off clock. Therefore, during the enable period of the PDRW control signal, the MUX1 508 and the MUX2 510 can repeatedly output the on clock and the off clock which are stored in the first buffer 504 and the second buffer 506, respectively, during every horizontal period).
(c) A gate shift register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode, and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode (see figures 1 and 6; paragraphs 61-63); (Read as level shifter IC 500. The first buffer 504 and the second buffer 506 store the on clock and the off clock fed back from the MUX1 508 and the MUX2 510, respectively, during every horizontal period in the form of data and update the on clock and the off clock. Therefore, during the enable period of the PDRW control signal, the MUX1 508 and the MUX2 510 can repeatedly output the on clock and the off clock which are stored in the first buffer 504 and the second buffer 506, respectively, during every horizontal period).
(d) Wherein adjacent gate clocks of the first-mode gate clocks have a phase difference equal to 1 horizontal period (see paragraphs 80-82; figure 3); (The difference is equal to units of 1H (1 horizontal period)).
(e) Wherein adjacent gate clock pairs of the second-mode gate clocks have a phase difference equal to 1 horizontal period and two gate clocks of the same gate clock pair are synchronized with each other (see paragraph 83); (A receiver RX of the level shifter IC 500-3 receives the first and second serial timing information STD1 and STD2 received from the timing controller 400-3 in synchronization with the clock CLK).
However, Cho et al does not specifically show that the first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock.
In related art, Baek et al shows that the first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock (see paragraph 108); (the 16-phase level shifter 15 receives the first reference signal GCLK and the second reference signal MCLK as an input from the timing controller 10).
Therefore, it would have been obvious to a person of ordinary skill in the art to incorporate the level shifter of Baek et al into the gate driver of Cho et al in order to output 16 types of carry clock signals (see Baek et al; paragraph 108).
However, Cho et al, in view of Baek et do not specifically show that the two gate clocks of the same gate clock pair are synchronized with each other to have the same phase to simultaneously scan two gate lines.
In related art, Kim et al shows that the two gate clocks of the same gate clock pair are synchronized with each other to have the same phase to simultaneously scan two gate lines (see figures 5 and 8; also see paragraphs 43-45); (Figure 8 shows that CLK1 and CLK2 have the same phase).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Kim et al into the teaching of Cho et al and Baek et al in order to the gate lines can be scanned simultaneously (See Kim et al; paragraphs 43-45).
Claims 3 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (Publication number: US 2019/0197964) in view of Baek et al (Publication number: US 2022/0208111) and Kim et al in view of Choi et al (Publication number: US 2022/0189407).
Consider Claims 3 and 11, Choi et al in view of Baek et al, and Kim et al do not specifically show that the gate shift register comprises a plurality of stages connected to one another, and wherein each of the plurality of stages comprises: a node control circuit configured to control a Q node and a QB node; and four scan output circuits and one carry output circuit configured to share the Q node and the QB node.
In related art, Choi et al shows that the gate shift register comprises a plurality of stages connected to one another, and wherein each of the plurality of stages comprises: a node control circuit configured to control a Q node and a QB node; and four scan output circuits and one carry output circuit configured to share the Q node and the QB node (see figures 1 and 5; and paragraphs 157-158).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Choi et al into the teaching of Cho et al and Baek et al, and Kim et al in order to fully swing signals output from the output nodes (see Choi et al; paragraphs 156-158).
Allowable Subject Matter
Claims 2, 4-8, 10, and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 05/07/2026
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