NON-FINAL OFFICE ACTION
REISSUE OF U.S. PATENT NO. 11,487,610
TABLE OF CONTENTS
1. ACKNOWLEDGEMENTS 3
2. ADDITIONAL TERMS 4
3. REISSUE PROCEDURAL REMINDERS 5
4. OTHER PROCEEDINGS 6
5. STATUS OF CLAIMS 6
6. RESTRICTION 6
7. PRIORITY AND AIA STATUS 10
8. INFORMATION CONSIDERED 11
9. PRIOR ART CITED 11
10. OWNERSHIP 11
11. DECLARATION 12
12. DRAWINGS 12
13. BROADEST REASONABLE INTERPRETATION (BRI) 13
14. CLAIM INTERPRETATION UNDER 35 USC § 112(f) 17
14.1. Functional Phrase #1 or FP#1 19
14.1.1. Prong (A) 20
14.1.2. Prong (B) 22
14.1.3. Prong (C) 23
14.1.4. Corresponding Structure for Functional Phrase #1 23
14.2. Functional Phrase #2 or FP#2 26
14.2.1. Prong (A) 27
14.2.2. Prong (B) 28
14.2.3. Prong (C) 28
14.2.4. Corresponding Structure for FP#2 29
14.3. Functional Phrase #3 or FP#3 30
14.3.1. Prong (A) 31
14.3.2. Prong (B) 32
14.3.3. Prong (C) 32
14.3.4. Corresponding Structure for FP#3 32
14.4. Functional Phrase #4 or FP#4 33
14.4.1. Prong (A) 34
14.4.2. Prong (B) 35
14.4.3. Prong (C) 35
14.4.4. Corresponding Structure for FP#4 35
14.5. Functional Phrase #5 or FP#5 36
14.5.1. Prong (A) 37
14.5.2. Prong (B) 38
14.5.3. Prong (C) 38
14.5.4. Corresponding Structure for FP#5 38
14.6. Functional Phrase #6 or FP#6 39
14.6.1. Prong (A) 40
14.6.2. Prong (B) 41
14.6.3. Prong (C) 41
14.6.4. Corresponding Structure for FP#6 41
14.7. Functional Phrase #7 or FP#7 42
14.7.1. Prong (A) 42
14.7.2. Prong (B) 44
14.7.3. Prong (C) 44
14.7.4. Corresponding Structure for FP#7 44
15. CLAIM REJECTIONS – 35 USC § 251 (Defective Declaration) 45
16. CLAIM REJECTIONS – 35 USC § 112(b) 45
16.1. Insufficient Disclosure Of Corresponding Structure 45
16.2. Conclusion of 35 USC § 112(b) Rejection 46
17. ALLOWABLE SUBJECT MATTER 47
18. CONCLUSION 47
ACKNOWLEDGEMENTS
This non-final Office action addresses U.S. reissue application No. 18/932,434 (“Instant Application”). Based upon a review of the Instant Application, the actual filing date is 30 October 2024 (“Actual Filing Date”).
The Instant Application is a reissue application of U.S. Patent No. 11,487,610 (“Patent Under Reissue” or “'610 Patent”) titled “METHODS FOR PARITY ERROR ALERT TIMING INTERLOCK AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME.”
An application for the Patent Under Reissue was filed on 09 May 2018 (“Base Application Filing Date”) and assigned by the Office non-provisional U.S. patent application number 15/975,703 (“Base Application” or “'703 Application”) and issued on 01 November 2022 with claims 1–20 (“Originally Patented Claims”).
ADDITIONAL TERMS
The following terms may appear in this Office action and, unless expressly noted otherwise, are defined as follows:
“POSITA” refers to a Person of Ordinary Skill in the Art.
“BRI” refers to Broadest Reasonable Interpretation.
“MPEP” refers to Manual of Patent Examining Procedure, Ninth Edition, Rev. 01.2024.
“IFW” refers to Image File Wrapper.
“35 USC” refers to Title 35 of the United States Code.
“37 CFR” refers to Title 37 of the Code of Federal Regulations.
“AIA ” refers to America Invents Act.
“Original Application” means the prosecution history of the Base Application, including the applications in the patent family’s entire prosecution history. See MPEP § 1412.02.
“Original Disclosure” means the substantive sections of the Base Application (i.e., the abstract, drawings, specification, and original claims) that were present in the Base Application on the Base Application Filing Date.
“Applicant” (uppercase) refers to the Applicant of the Instant Application.
“applicant” (lowercase) refers to an applicant(s) generally.
“patent owner” (lowercase) refers to a patent owner(s) generally and not the Applicant.
“Examiner” (uppercase) refers to the Examiner of the Instant Application.
“examiner” (lowercase) refers to an examiner(s) generally, e.g. the examiner of the Base Application, or any examiner(s) other than the Examiner.
REISSUE PROCEDURAL REMINDERS
Disclosure of other proceedings. Applicant is reminded of the continuing obligation under 37 CFR § 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which the Patent Under Reissue is or was involved. These proceedings would include interferences, reissues, reexaminations, and litigation.
Disclosure of material information. Applicant is further reminded of the continuing obligation under 37 CFR § 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue appli-cation.
These disclosure obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Manner of making amendments. Applicant is reminded that changes to the Instant Application must comply with 37 CFR § 1.173, such that all amendments are made in respect to the Patent Under Reissue as opposed to any prior changes entered in the Instant Application. All added material must be underlined, and all omitted material must be enclosed in brackets, in accordance with Rule 173. Applicant may submit an appendix to any response in which claims are marked up to show changes with respect to a previous set of claims, however, such claims should be clearly denoted as “not for entry.”
OTHER PROCEEDINGS
Based upon the Examiner’s independent review of the Patent Under Reissue itself and its prosecution history, the Examiner cannot locate any concurrent proceedings before the Office, ongoing litigation, previous reexaminations (ex parte or inter partes), supplemental examinations, or certificates of correction regarding the Patent Under Reissue.
STATUS OF CLAIMS
Claims 1–22, as set forth in the preliminary amendment filed on the Actual Filing Date, are currently pending (“Pending Claims”).
Claims 9–19 and currently examined (“Examined Claims”).
Claims 1–8 and 20–22 are withdrawn, as noted below.
Regarding the Examined Claims and as a result of this Office action:
Claims 9–19 are rejected under 35 USC § 251.
Claims 9–19 are rejected under 35 USC § 112(b).
RESTRICTION
Restriction to one of the following inventions is required under 35 USC § 121:
I. Claims 1–8 and 21–22, drawn to a method for operating a memory device.
II. Claims 9–19, drawn to a memory device.
III. Claim 20, drawn to a memory device.
The inventions are independent or distinct, each from the other because:
Inventions I and II/III are related as process and apparatus for its practice. The inventions are distinct if it can be shown that either: (1) the process as claimed can be practiced by another and materially different apparatus or by hand, or (2) the apparatus as claimed can be used to practice another and materially different process. (MPEP § 806.05(e)). In this case, both the apparatus of Invention II and the apparatus of Invention III can be used to practice another and materially different process.
Inventions II and III are directed to related products. The related inventions are distinct if: (1) the inventions as claimed are either not capable of use together or can have a materially different design, mode of operation, function, or effect; (2) the inventions do not overlap in scope, i.e., are mutually exclusive; and (3) the inventions as claimed are not obvious variants. See MPEP § 806.05(j). In the instant case, the inventions as claimed have a materially different design, mode of operation, function, and/or effect. For example, in claim 9 the memory device functions to “generate an internal operations done signal when no internal memory operations are in progress” and “generate a parity error alert signal based on […] the internal operations done signal;” however, in claim 20 the memory device functions to “complet[e] one or more internal memory operations in progress” and “disabl[e] the parity error alert signal in response to detecting that the period of time substantially equal to the parity error alert pulse width value has elapsed.” Therefore, Invention I and Invention II are not capable of use together and/or have a materially different design, mode of operation, function, and/or effect. Furthermore, the inventions as claimed do not encompass overlapping subject matter and there is nothing of record to show them to be obvious variants.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply: the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries).
For restriction in a reissue application, 37 CFR § 1.176(b) allows “[r]estriction between subject matter of the original patent claims and previously unclaimed subject matter.” The above restriction demonstrates that newly submitted claims 1–8 and 20–22 are directed to an invention(s) that is independent or distinct from the Invention II, as originally claimed. The Examiner also finds that newly submitted claims 1–8 and 20–22 include previously unclaimed subject matter. First, original patent claim 1 was to a method comprising a step of “disabling the parity error alert signal in response to detecting that no memory operations are in progress” (emphasis added). However, newly submitted claim 1 now claims a method including a step of “completing memory operations in progress” and “disabling the parity error alert signal in response to detecting that the period of time […] has elapsed.” This new subject matter of amended claim 1 represents a new process with new method steps previously unclaimed. Second, original patent claim 20 was to a memory device comprising a “means for generating a parity error alert signal […].” However, newly submitted claim 20 now claims a “means for disabling the parity error alert signal in response to detecting that the period of time […] has elapsed.” This new subject matter of amended claim 20 represents a new means-plus-function element previously unclaimed.
Therefore, for the reasons given above, newly submitted claims 1–8 and 20–22 include subject matter previously unclaimed and are directed to an invention(s) that is independent or distinct from the invention originally claimed.
Since Applicant has not filed a disclaimer of all the patent claims (see MPEP § 1450 I. for a discussion of the requisite disclaimer)1, the subject matter of the original patent claims 9–19 has been constructively elected for prosecution on the merits. See MPEP § 1450. Accordingly, claims 1–8 and 20–22 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR § 1.176(b).
In accordance with MPEP § 1450, the Examiner suggests Applicant may file a divisional reissue application(s) directed to the constructively non-elected invention(s) of claims 1–8 and 20–22. Also in accordance with MPEP § 1450, Applicant is hereby informed, if the original patent claims 9–19 are found allowable and no error (other than the failure to present the non-elected claims) is being corrected in the reissue application under examination, and a divisional application has been filed for the non-elected claims, further action in the Instant Application will be suspended, pending resolution of the divisional application. Also in accordance with MPEP § 1450, the non-elected claims will only be examined if filed in a divisional reissue application (see MPEP § 1450).
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR § 1.144. If claims are subsequently added, Applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should Applicant traverse on the ground that the inventions are not patentably distinct, Applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the Examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under pre-AIA 35 USC § 103(a) of the other invention.
PRIORITY AND AIA STATUS
Domestic Priority. Based upon a review of the Instant Application and the Patent Under Reissue, the Examiner finds that in the Instant Application there is not a claim for benefit of domestic priority under 35 USC §§ 120 or 119(e). Because the Instant Application does not claim benefit of domestic priority, the effective U.S. filing date of the Instant Application is the Base Application Filing Date.
AIA Status. Because the Instant Application does not contain a claim having an effective date before March 16, 2013, the AIA provisions apply. In the event the determination of the status of the application as subject to AIA 35 USC §§ 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
INFORMATION CONSIDERED
The IDS filed 20 November 2024 is in compliance with the provisions of 37 CFR § 1.97. Accordingly, the IDS filed 20 November 2024 has been considered by the Examiner as noted on the attached annotated document.
In accordance with MPEP § 1406, the Examiner has reviewed and considered the prior art cited or “of record” in the original prosecution of the Patent Under Reissue. Applicant is reminded that a listing of the information cited or “of record” in the original prosecution of the Patent Under Reissue has been considered in the Instant Application and need not be resubmitted.
PRIOR ART CITED
The following prior art patents and printed publications are cited below:
U.S. Patent 9,389,953 (“Choi”).
The prior art made of record and considered pertinent to Applicant’s disclosure, but not relied upon to reject the claims in this Office action, is listed on the attached document titled “Notice of Reference Cited” (PTO-892). Unless expressly noted otherwise by the Examiner, all documents listed on the PTO-892 are cited in their entirety.
OWNERSHIP
This application is objected to under 37 CFR § 1.172(a) as the assignee has not established its ownership interest in the patent “by filing a submission in accordance with the provisions of § 3.73(c) of this chapter.” The Statement Under 37 CFR § 3.73(c) filed on the Actual Filing Date is objected to as not complying with 37 CFR § 3.73(c)(1). In particular, the Examiner finds that the Statement Under 37 CFR § 3.73(c) does not include the reel/frame number for the assignment from Micron Technology, Inc. to Lodestar Licensing Group LLC. The Examiner finds that the showing of ownership is otherwise in compliance. For the above reasons, the Applicant is required to file a new showing of ownership correcting the above noted deficiency.
DECLARATION
The reissue declaration filed on the Actual Filing Date (“October 2024 Declaration”) is defective because the error which is relied upon to support the Instant Application is not an error upon which the Instant Application can be based. See 37 CFR § 1.175 and MPEP § 1414.
According to the error statement in the October 2024 Declaration, the Instant Application seeks to broaden the Originally Patented Claims by amending at least independent claim 1. However, independent claim 1, and dependents thereof, and independent claim 20 are drawn to a non-elected invention and are held in abeyance in a withdrawn status. Accordingly, only original patent claims 9–19 remain pending and under consideration, and therefore no error correctable via reissue is presented in the Instant Application. Pursuant to 37 CFR § 1.175(d), Applicant must identify an error being relied upon as a basis for reissue since the error previously identified in the October 2024 Declaration is no longer being relied upon as a basis for reissue.
DRAWINGS
Figures 3A, 3B, and 4 are objected to under 37 CFR § 1.83(a) because they include illegible text.
Moreover, figures 1–6 are objected to under 37 CFR § 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “configur[ation]” of each of the “internal operations in progress detector” (claim 9), the “parity error alert signal detector” (claim 9), the “precharge generator” (claim 14), the “sequential logic” (claim 14), the “combinational logic” (claim 14), and the “logic” (claim 18) must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR § 1.173(b)(3) are required in reply to the Office action to avoid abandonment of the application. Any changes to a patent drawing must be submitted as a replacement sheet of drawings which shall be an attachment to the amendment document. Any replacement sheet of drawings must be in compliance with § 1.84 and shall include all of the figures appearing on the original version of the sheet, even if only one figure is amended. Amended figures must be identified as “Amended,” and any added figure must be identified as “New.” In the event that a figure is canceled, the figure must be surrounded by brackets and identified as “Canceled.” All changes to the drawing(s) shall be explained, in detail, beginning on a separate sheet accompanying the papers including the amendment to the drawings. If the changes are not accepted by the Examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
BROADEST REASONABLE INTERPRETATION (BRI)
During examination, claims are given the broadest reasonable interpretation consistent with the specification and limitations in the specification are not read into the claims. See MPEP § 2111, MPEP § 2111.01 and In re Yamamoto et al., 222 USPQ 934 (Fed. Cir. 1984). Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. See MPEP § 2111.01 I. Moreover, it is improper to import claim limitations from the specification, e.g., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP § 2111.01 II. Therefore, unless otherwise noted below, the Examiner will interpret the limitations of the Pending Claims using the broadest reasonable interpretation.
After careful review of the original specification, the Examiner finds he cannot locate any lexicographic definitions (either express lexicographic definitions or implied lexicographic definitions) with the required clarity, deliberateness, and precision. Because the Examiner cannot locate any lexicographic definitions with the required clarity, deliberateness, and precision, the Examiner concludes that Applicant is not his own lexicographer. See MPEP § 2111.01 IV.
The Examiner hereby adopts the following interpretations under the broadest reasonable interpretation standard. In accordance with In re Morris, 127 F.3d 1048, 1056, 44 USPQ2d 1023, 1029 (Fed. Cir. 1997), the Examiner points to these other sources to support his interpretation of the claims.2 Additionally, these interpretations are only a guide to claim terminology since claim terms must be interpreted in context of the surrounding claim language. Finally, the following list is not intended to be exhaustive in any way:
parity error (n.) “An error in parity that indicates an error in transmitted data or in data stored in memory. If a parity error occurs in communications, all or part of a message must be retransmitted; if a parity error occurs in RAM, the computer usually halts. See also parity, parity bit.” Microsoft Computer Dictionary (5th Ed. 2002).
parity bit (n.) “An extra bit used in checking for errors in groups of data bits transferred within or between computer systems. With PCs, the term is frequently encountered in modem-to-modem communications, in which a parity bit is often used to check the accuracy with which each character is transmitted, and in RAM, where a parity bit is often used to check the accuracy with which each byte is stored.” Microsoft Computer Dictionary (5th Ed. 2002).
parity (n.) “The quality of sameness or equivalence, in the case of computers usually referring to an error-checking procedure in which the number of 1s must always be the same—either even or odd—for each group of bits transmitted without error. If parity is checked on a per-character basis, the method is called vertical redundancy checking, or VRC; if checked on a block-by-block basis, the method is called longitudinal redundancy checking, or LRC. In typical modem-to-modem communications, parity is one of the parameters that must be agreed upon by sending and receiving parties before transmission can take place. See the table [P.1]. See also parity bit, parity check, parity error.” Microsoft Computer Dictionary (5th Ed. 2002).
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detector (n.) “One that detects, especially a mechanical, electrical, or chemical device that automatically identifies and records or registers a stimulus, such as an environmental change in pressure or temperature, an electric signal, or radiation from a radioactive material.” American Heritage Dictionary of the English Language (3rd Ed. 1992).
signal (n.) “1. Any electrical quantity, such as voltage, current, or frequency, that can be used to transmit information. 2. A beep or tone from a computer’s speaker or a prompt displayed on screen that tells a user that the computer is ready to receive input.” Microsoft Computer Dictionary (5th Ed. 2002).
generator (n.) “1. a. One that generates, especially a machine that converts mechanical energy into electrical energy. b. An apparatus that generates vapor or gas. 2. A circuit that generates a specified waveform. 3. Mathematics. See generatrix. 4. Computer Science. A program that produces specific programs from the definition of an operation.” American Heritage Dictionary of the English Language (3rd Ed. 1992).
timer (n.) “A register (high-speed memory circuit) or a special circuit, chip, or software routine used to measure time intervals. A timer is not the same as the system clock, although its pulses can be derived from the system clock frequency.” Microsoft Computer Dictionary (5th Ed. 2002).
logic (n.)
(1) “In programming, the assertions, assumptions, and operations that define what a given program does. Defining the logic of a program is often the first step in developing the program’s source code.” Microsoft Computer Dictionary (5th Ed. 2002); and
(2) “5. Computer Science. a. The nonarithmetic operations performed by a computer, such as sorting, comparing, and matching, that involve yes-no decisions. b. Computer circuitry. c. Graphic representation of computer circuitry.” American Heritage Dictionary of the English Language (3rd Ed. 1992).
compute (vb.) “1. To perform calculations. 2. To use a computer or cause it to do work.” Microsoft Computer Dictionary (5th Ed. 2002).
computer (n.) “Any device capable of processing information to produce a desired result. No matter how large or small they are, computers typically perform their work in three well-defined steps: (1) accepting input, (2) processing the input according to predefined rules (programs), and (3) producing output. There are several ways to categorize computers, including class (ranging from microcomputers to supercomputers), generation (first through fifth generation), and mode of processing (analog versus digital).” Microsoft Computer Dictionary (5th Ed. 2002).
CLAIM INTERPRETATION UNDER 35 USC § 112(f)
The following is a quotation of 35 USC § 112(f):
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
“Application of 35 U.S.C. 112(f) is driven by the claim language, not by applicant’s intent or mere statements to the contrary included in the specification or made during prosecution. See In re Donaldson Co., 16 F.3d at 1194, 29 USPQ2d at 1850 (stating that 35 U.S.C. 112, sixth paragraph ‘merely sets a limit on how broadly the PTO may construe means-plus-function language under the rubric of reasonable interpretation’).” MPEP § 2181 I.
“A claim limitation is presumed to invoke 35 U.S.C. 112(f) when it explicitly uses the term ‘means’ or ‘step’ and includes functional language. The presumption that 35 U.S.C. 112(f) applies is overcome when the limitation further includes the structure, material or acts necessary to perform the recited function.” MPEP § 2181 I.
“By contrast, a claim limitation that does not use the term ‘means’ or ‘step’ will trigger the rebuttable presumption that 35 U.S.C. 112(f) does not apply. […]. Even in the face of this presumption, the examiner should nonetheless consider whether the presumption is overcome. The presumption that 35 U.S.C. 112(f) does not apply to a claim limitation that does not use the term ‘means’ is overcome when ‘the claim term fails to recite sufficiently definite structure or else recites function without reciting sufficient structure for performing that function.’ Williamson[ v. Citrix Online, LLC], 792 F.3d [1339,] 1349[…] (Fed. Cir. 2015) (en banc) (quoting Watts v. XL Systems, Inc., 232 F.3d 877, 880, 56 USPQ2d 1836, 1838 (Fed. Cir. 2000).” MPEP § 2181 I. (internal quotations of Williamson removed).
However, “section 112, ¶ 6, […] with respect to steps, […] is implicated only when steps plus function without acts are present. […] claiming a step by itself, or even a series of steps, does not implicate section 112, ¶ 6.” O.I. Corp. v. Tekmar Co., 115 F.3d 1576, 1583 (Fed. Cir. 1997) (emphasis in original).
In other words, “[m]erely claiming a step without recital of a function is not analogous to a means plus a function.” O.I. Corp. v. Tekmar Co., id. (emphasis added).
Accordingly, examiners will apply 35 U.S.C. 112(f) to a claim limitation if it meets the following 3-prong analysis:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
MPEP § 2181 I.
“Each claim must be independently reviewed in order to determine if it is subject to the requirements of section 112, ¶ 6.” O.I. Corp. v. Tekmar Co., id.
In view of the above MPEP and Federal Circuit guidance, the Examiner has evaluated each claim under the 3-Prong Analysis set forth in MPEP § 2181 I. to determine whether any of the claim elements are subject to the requirements of § 112(f). In the sections that follow, the Examiner will identify each claim limitation that is subject to the requirements of § 112(f).
Functional Phrase #1 or FP#1
The first functional phrase to be considered is “internal operations in progress detector configured to determine if internal memory operations are in progress and generate an internal operations done signal when no internal memory operations are in progress, wherein the internal memory operations were initiated before the parity error detector generates the parity error signal.” Claim 9 (“Functional Phrase #1” or “FP#1”).
For purpose of discussion below, FP#1 is broken into the following three parts:
“internal operations in progress detector” (“Introductory Phrase of FP#1);
“configured to” (“Linking Phrase of FP#1); and
“[1] determine if internal memory operations are in progress and [2] generate an internal operations done signal when no internal memory operations are in progress, wherein the internal memory operations were initiated before the parity error detector generates the parity error signal” (“Function of FP#1”).
Prong (A)
In accordance with the MPEP, Prong (A) requires “the claim limitation uses the term ‘means’ […] or a term used as a substitute for ‘means’ that is a generic placeholder […] for performing the claimed function.”3 MPEP § 2181 I. (“Prong (A)”).4
As an initial matter, the Examiner finds that FP#1 does not use the term “means.” Therefore the issue arising under Prong (A) then becomes whether or not the presumption that 35 USC § 112(f) is not invoked can be overcome. “Even in the face of this presumption, the examiner should nonetheless consider whether the presumption is overcome.” MPEP § 2181 I.
With respect to the presumption that 35 USC § 112(f) is not invoked, “[t]he question is not whether a claim term recites any structure but whether it recites sufficient structure—a claim term is subject to § 112 ¶ 6 if it recites ‘function without reciting sufficient structure for performing that function.’ Williamson, 792 F.3d at 1348 (emphasis added) (quoting Watts, 232 F.3d at 880).” Egenera, Inc. v. Cisco Systems, Inc., 972 F.3d 1367, 1374 (Fed. Cir. 2020).
“And, again, the question is not whether [the claim term] is utterly devoid of structure but whether the claim term recites sufficient structure to perform the claimed functions.” Egenera at 1374 (emphasis added).
To help understand the meaning of “sufficient structure,” the MPEP and the Federal Circuit have stated that:
Sufficient structure exists when the claim language specifies the exact structure that performs the function in question without need to resort to other portions of the specification or extrinsic evidence for an adequate understanding of the structure.
See MPEP § 2181 I. quoting TriMed, Inc. v. Stryker Corp., 514 F.3d 1256, 1259–60 (Fed. Cir. 2008).
Moreover, in assessing whether or not FP#1 meets Prong (A), the Examiner must not only consider the Introductory Phrase of FP#1 in isolation, but the entire FP#1 including the Function of FP#1. See MTD Prods. Inc. v. Iancu, 933 F.3d 1336, 1342 (Fed. Cir. 2019) (“In assessing whether the claim limitation is in means-plus-function format, we do not merely consider the introductory phrase (e.g., ‘mechanical control assembly’) in isolation, but look to the entire passage including functions performed by the introductory phrase.”).
The Examiner has looked to both general and subject matter specific dictionaries5 and finds no evidence that the Introductory Phrase of FP#1, i.e., the term “internal operations in progress detector,” has achieved recognition as a term denoting structure for performing the Function of FP#1. See above section titled “BROADEST REASONABLE INTERPRETATION (BRI).”
Similarly, upon review of the record (including the prior art of record), the Examiner finds no evidence that the term “internal operations in progress detector” has achieved recognition as denoting structure for performing the Function of FP#1.
Therefore, based upon consultation of dictionaries and a review of the record, the Examiner concludes that the term “internal operations in progress detector” is not an art-recognized structure to perform the Function of FP#1, and claim 9 does not recite any other structure that would perform this claimed function.
Therefore, because the ordinary meaning of “internal operations in progress detector” is not an art-recognized structure to perform the Function of FP#1, the Examiner concludes that the ordinary meaning of the Introductory Phrase of FP#1 does not include sufficient structure for performing the Function of FP#1. See at least TriMed, as cited above.
Therefore, the Examiner concludes that “internal operations in progress detector” is a generic placeholder for performing the Function of FP#1, and therefore FP#1 meets Prong (A).
Prong (B)
In accordance with the MPEP, Prong (B) requires “the term ‘means’ […] or the generic placeholder is modified by functional language, typically, but not always linked by the transition word ‘for’ […] or another linking word or phrase, such as ‘configured to’ or ‘so that.’” MPEP § 2181 I. (“Prong (B)”).
Based upon the claim language itself, the Examiner finds that the Introductory Phrase of FP#1 (generic placeholder) is modified by the Function of FP#1 (functional language) linked by the Linking Phrase of FP#1. Therefore, the Examiner concludes that FP#1 meets Prong (B).
Prong (C)
In accordance with the MPEP, Prong (C) requires “the term ‘means’ […] or the generic placeholder is not modified by sufficient structure […] for performing the claimed function.” MPEP § 2181 I. (“Prong (C)”).
Based upon a review of FP#1, and for reasons already discussed above, the Examiner finds that FP#1 does not contain sufficient structure for performing the entire Function of FP#1. Therefore, the Examiner concludes that the Introductory Phrase of FP#1 is not modified by sufficient structure (as defined by the MPEP and the Federal Circuit, supra) for performing the Function of FP#1.
Because FP#1 does not contain sufficient structure for performing the entire claimed function, the Examiner concludes that FP#1 meets Prong (C). Because FP#1 meets the 3 Prong Analysis as set forth in MPEP § 2181 I., the Examiner concludes that FP#1 invokes § 112(f).
Corresponding Structure for Functional Phrase #1
“The next step in construing a means-plus-function claim limitation is to look to the specification and identify the corresponding structure for that function.” In re Aoyama, 656 F3d 1293, 1297 (Fed. Cir. 2011) quoting Golight, Inc. v. Wal-Mart Stores, Inc., 355 F.3d 1327, 1333 (Fed. Cir. 2004). “Under this second step, structure disclosed in the specification is ‘corresponding’ structure only if the specification or prosecution history clearly links or associates that structure to the function recited in the claim.” Aoyama, 656 F3d at 1297 quoting Med. Instrumentation & Diagnostics Corp. v. Elekta AB, 344 F.3d 1205, 1210 (Fed. Cir. 2003).
Furthermore, if the claimed phase is meant to cover software, “[i]t is well-established that the corresponding structure for a function performed by a software algorithm is the algorithm itself.” EON Corp. IP Holdings LLC v. AT&T Mobility LLC, 785 F.3d 616, 621, 114 USPQ2d 1711, 1714 (Fed. Cir. 2015). In other words, “[i]f special programming is required for a general-purpose computer to perform the corresponding claimed function, then the default rule requiring disclosure of an algorithm applies.” Ergo Licensing, LLC v. CareFusion 303, Inc., 673 F.3d 1361, 1365 (Fed. Cir. 2012).
Based upon a review of the Patent Under Reissue and the Original Disclosure, the Examiner is unable to clearly link or associate the Function of FP#1 to sufficient corresponding structure found in the specification. Recall that the Function of FP#1 refers to “[1] determine if internal memory operations are in progress and [2] generate an internal operations done signal when no internal memory operations are in progress, wherein the internal memory operations were initiated before the parity error detector generates the parity error signal,” as recited by claim 9.
First, regarding part [1] of the Function of FP#1, the disclosure states that “[t]he internal parity error signal 610 is also received by a command in-progress signal generator block 630 which generates an internal command in-progress signal 632 indicating that internal commands are in progress.” See '610 Patent at C9:L53–56. See also figure 6 of the '610 Patent (reproduced below).
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Figure 6 of the '610 Patent
However, while the '610 Patent describes “block 630” as “generat[ing] an internal command in-progress signal 632 indicating that internal commands are in progress” (id.), the Examiner finds that “block 630” – a black-box structure in figure 6 – is not clearly linked and associated with “determine if internal memory operations are in progress […] wherein the internal memory operations were initiated before the parity error detector generates the parity error signal” (i.e., part [1] of the Function of FP#1), nor is it sufficient corresponding structure for performing “determine if internal memory operations are in progress […] wherein the internal memory operations were initiated before the parity error detector generates the parity error signal.”
Second, regarding part [2] of the Function of FP#1, the disclosure states “[a]n internal operations-done detector block 638 determines whether there are pending internal operations, for example, whether precharge signal 636 has been activated, and notifies the parity error alert signal generator 680 using a signal 639.” See '610 Patent at C10:L1–5. See also figure 6 of the '610 Patent (reproduced above).
However, while the '610 Patent describes “block 638” as “notif[ying] the parity error alert signal generator 680 using a signal 639,” the Examiner finds that “block 638” – another black-box structure in figure 6 – is not sufficient corresponding structure for performing “generate an internal operations done signal when no internal memory operations are in progress, wherein the internal memory operations were initiated before the parity error detector generates the parity error signal” (i.e., part [2] of the Function of FP#1).
Because each of the Patent Under Reissue and the Original Disclosure fails to clearly link or associate the Function of FP#1 to sufficient corresponding structure, claim 9 is indefinite under 35 USC § 112(b). A rejection under 35 USC § 112(b) is set forth below for claim 9. For purposes of applying the prior art, the Examiner will interpret the structure of FP#1 to include any hardware alone or in combination with software/firmware that is capable of accomplishing the Function of FP#1.
Functional Phrase #2 or FP#2
The second functional phrase to be considered is “parity error alert signal generator […] configured to generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal.” Claim 9 (“Functional Phrase #2” or “FP#2”).
For purpose of discussion below, FP#2 is broken into the following three parts:
“parity error alert signal generator” (“Introductory Phrase of FP#2);
“configured to” (“Linking Phrase of FP#2); and
“generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal” (“Function of FP#2”).
Prong (A)
As an initial matter, the Examiner finds that FP#2 does not use the term “means.” Therefore the issue arising under Prong (A) then becomes whether or not the presumption that 35 USC § 112(f) is not invoked can be overcome.
Moreover, in assessing whether or not FP#2 meets Prong (A), the Examiner must not only consider the Introductory Phrase of FP#2, but the entire FP#2 including the Function of FP#2.
Similar to the above analysis of FP#1, the Examiner has looked to both general and subject matter specific dictionaries and finds no evidence that the term “parity error alert signal generator” has achieved recognition as a term denoting structure to perform the Function of FP#2. See above section titled “BROADEST REASONABLE INTERPRETATION (BRI).”
Similarly, upon review of the record (including the prior art of record), the Examiner finds no evidence that the term “parity error alert signal generator” has achieved recognition as denoting structure to perform the Function of FP#2.
Therefore, based upon consultation of dictionaries and a review of the record, the Examiner concludes that the term “parity error alert signal generator” is not an art-recognized structure to perform the Function of FP#2, and claim 9 does not recite any other structure that would perform this claimed function.
Therefore, because the ordinary meaning of “parity error alert signal generator” is not an art-recognized structure to perform the Function of FP#2, the Examiner concludes that the ordinary meaning of the Introductory Phrase of FP#2 does not include sufficient structure for performing the Function of FP#2. See at least TriMed, as cited above.
Therefore, the Examiner concludes that “parity error alert signal generator” is a generic placeholder for performing the Function of FP#2, and therefore FP#2 meets Prong (A).
Prong (B)
Based upon the claim language itself, the Examiner finds that the Introductory Phrase of FP#2 (generic placeholder) is modified by the Function of FP#2 (functional language) linked by the Linking Phrase of FP#2. Therefore, the Examiner concludes that FP#2 meets Prong (B).
Prong (C)
Based upon a review of FP#2, and for reasons already discussed above, the Examiner finds that FP#2 does not contain sufficient structure for performing the entire Function of FP#2. Therefore, the Examiner concludes that the Introductory Phrase of FP#2 is not modified by sufficient structure (as defined by the MPEP and the Federal Circuit, supra) for performing the Function of FP#2.
Because FP#2 does not contain sufficient structure for performing the entire claimed function, the Examiner concludes that FP#2 meets Prong (C). Because FP#2 meets the 3 Prong Analysis as set forth in MPEP § 2181 I., the Examiner concludes that FP#2 invokes § 112(f).
Corresponding Structure for FP#2
Based upon a review of the Patent Under Reissue and the Original Disclosure, the Examiner is unable to clearly link or associate the Function of FP#2 to sufficient corresponding structure found in the specification. Recall that the Function of FP#2 refers to “generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal.”
First, Applicant’s specification discloses “The internal parity error signal 610 is received by a parity error alert signal generator block 680 which generates an external parity error alert signal 698 (ALERT_n) to the host.” See '610 Patent at C9:L43–46. However, while the '610 Patent describes “block 680” as “generat[ing] an external parity error alert signal 698 (ALERT_n)” (id.), the Examiner finds that “block 698” – a black-box structure in figure 6 – is not clearly linked and associated with “generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal” (i.e., the Function of FP#2), nor is it sufficient corresponding structure for performing “generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal.”
Second, Applicant’s specification discloses “The parity error alert signal generator block 680 receives the internal parity error signal 610, the timer timeout indication signal 622 and the signal 639 indicating whether internal operations are done and deasserts the parity error alert signal […] if the timeout indication signal 622 indicates the timer has counted a tPAR_ALERT_PW time and signal 639 indicates that there are no pending internal operations.” See '610 Patent at C10:L5–13. However, while the '610 Patent describes “block 680” as “deassert[ing] the parity error alert signal” (id.), the Examiner finds that “block 698” – a black-box structure in figure 6 – is not clearly linked and associated with “generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal” (i.e., the Function of FP#2), nor is it sufficient corresponding structure for performing “generate a parity error alert signal based on the parity error signal, the timeout signal, and the internal operations done signal.”
Because each of the Patent Under Reissue and the Original Disclosure fails to clearly link or associate the Function of FP#2 to sufficient corresponding structure, claim 9 is indefinite under 35 USC § 112(b). A rejection under 35 USC § 112(b) is set forth below for claim 9. For purposes of applying the prior art, the Examiner will interpret the structure of FP#2 to include any hardware alone or in combination with software/firmware that is capable of accomplishing the Function of FP#2.
Functional Phrase #3 or FP#3
The third functional phrase to be considered is “precharge generator configured to receive a command in-progress signal and a precharge timer clock.” Claim 14 (“Functional Phrase #3” or “FP#3”).
For purpose of discussion below, FP#3 is broken into the following three parts:
“precharge generator” (“Introductory Phrase of FP#3);
“configured to” (“Linking Phrase of FP#3); and
“receive a command in-progress signal and a precharge timer clock” (“Function of FP#3”).
Prong (A)
As an initial matter, the Examiner finds that FP#3 does not use the term “means.” Therefore the issue arising under Prong (A) then becomes whether or not the presumption that 35 USC § 112(f) is not invoked can be overcome.
Moreover, in assessing whether or not FP#3 meets Prong (A), the Examiner must not only consider the Introductory Phrase of FP#3, but the entire FP#3 including the Function of FP#3.
Similar to the above analysis of FP#1, the Examiner has looked to both general and subject matter specific dictionaries and finds no evidence that the term “precharge generator” has achieved recognition as a term denoting structure to perform the Function of FP#3. See above section titled “BROADEST REASONABLE INTERPRETATION (BRI).”
Similarly, upon review of the record (including the prior art of record), the Examiner finds no evidence that the term “precharge generator” has achieved recognition as denoting structure to perform the Function of FP#3.
Therefore, based upon consultation of dictionaries and a review of the record, the Examiner concludes that the term “precharge generator” is not an art-recognized structure to perform the Function of FP#3, and claim 14 does not recite any other structure that would perform this claimed function.
Therefore, because the ordinary meaning of “precharge generator” is not an art-recognized structure to perform the Function of FP#3, the Examiner concludes that the ordinary meaning of the Introductory Phrase of FP#3 does not include sufficient structure for performing the Function of FP#3. See at least TriMed, as cited above.
Therefore, the Examiner concludes that “precharge generator” is a generic placeholder for performing the Function of FP#3, and therefore FP#3 meets Prong (A).
Prong (B)
Based upon the claim language itself, the Examiner finds that the Introductory Phrase of FP#3 (generic placeholder) is modified by the Function of FP#3 (functional language) linked by the Linking Phrase of FP#3. Therefore, the Examiner concludes that FP#3 meets Prong (B).
Prong (C)
Based upon a review of FP#3, and for reasons already discussed above, the Examiner finds that FP#3 does not contain sufficient structure for performing the entire Function of FP#3. Therefore, the Examiner concludes that the Introductory Phrase of FP#3 is not modified by sufficient structure (as defined by the MPEP and the Federal Circuit, supra) for performing the Function of FP#3.
Because FP#3 does not contain sufficient structure for performing the entire claimed function, the Examiner concludes that FP#3 meets Prong (C). Because FP#3 meets the 3 Prong Analysis as set forth in MPEP § 2181 I., the Examiner concludes that FP#3 invokes § 112(f).
Corresponding Structure for FP#3
Based upon a review of the Patent Under Reissue and the Original Disclosure, the Examiner is unable to clearly link or associate the Function of FP#3 to sufficient corresponding structure found in the specification. Recall that the Function of FP#3 refers to “receive a command in-progress signal and a precharge timer clock.”
Applicant’s specification discloses “The internal command in-progress signal 632, together with a latched array timer signal 646, is used by a precharge trigger block 634 to generate a precharge signal 636 used to precharge memory banks of memory device 100.” See '610 Patent at C9:L59–63. However, the Examiner finds that “block 634” – a black-box structure in figure 6 – is not sufficient corresponding structure for performing “receive a command in-progress signal and a precharge timer clock.”
Because each of the Patent Under Reissue and the Original Disclosure fails to clearly link or associate the Function of FP#3 to sufficient corresponding structure, claim 14 is indefinite under 35 USC § 112(b). A rejection under 35 USC § 112(b) is set forth below for claim 14. For purposes of applying the prior art, the Examiner will interpret the structure of FP#3 to include any hardware alone or in combination with software/firmware that is capable of accomplishing the Function of FP#3.
Functional Phrase #4 or FP#4
The fourth functional phrase to be considered is “sequential logic configured to latch the precharge timer clock in response to detecting that the command in-progress signal is asserted.” Claim 14 (“Functional Phrase #4” or “FP#4”).
For purpose of discussion below, FP#4 is broken into the following three parts:
“sequential logic” (“Introductory Phrase of FP#4);
“configured to” (“Linking Phrase of FP#4); and
“latch the precharge timer clock in response to det