DETAILED ACTION
The Examiner acknowledges the applicant's submission of the amendment dated 3/23/2026.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-12, 14, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Franaszek (US 5,761,536).
Regarding Claim 1, Franaszek teaches a method of storing a modified version of a variable length data block among a set of M variable length data blocks stored in a memory, wherein M is an integer greater than or equal to two (the M variable length data blocks stored in a memory corresponding to the compressed data blocks/cache lines stored in compressed main memory 108 of Fig. 1, C5 L12-18, and a cache line may be modified or ”changed,” C7 L8-21), wherein the set of M variable length data blocks are stored in the memory such that at least a portion of each variable length data block in the set is stored in a chunk of the memory allocated to that variable length data block (each full block portion of the variable length data block is stored in a block/chunk allocated for it at step 412 of Fig. 4, “N blocks are allocated to accommodate the full blocks needed to store the line,” C7 L53-59), and any remaining portions of the M variable length data blocks in the set are stored in a remainder section (the remainder section corresponding to the block which stores the “remainder of the line” along with the remaining portion of another previously-stored cache line, C7 L33-45), the method comprising:
receiving the modified version of the variable length data block in the set (a changed/modified cache line is received at step 400 of Fig. 4, C7 L8-21, also see C7 L22-31 indicating the cache line is of variable length);
storing a portion of the modified version of the variable length data block in the chunk of the memory allocated to the corresponding variable length data block in the set (each full block portion of the variable length data block is stored in a block/chunk allocated for it at step 412 of Fig. 4, “N blocks are allocated to accommodate the full blocks needed to store the line,” C7 L53-59); and
repacking any remaining portion of the modified version of the variable length data block in the remainder section along with the remaining portions of at least one other variable length data block in the set (the remaining portion of the modified version of the variable data length block is stored in a remainder section corresponding to the block which stores the “remainder of the line” along with the remaining portion of another previously-stored cache line, C7 L33-45).
Regarding Claim 4, the cited prior art teaches the method of claim 1, wherein repacking any remaining portion of the modified version of the variable length data block in the remainder section comprises:
reading the remaining portion of the at least one other variable length data block in the set from the remainder section (step 408 of Fig. 4, data from other remaining portions are read to check the size to see where the remaining portion will fit, C7 L33-45);
forming a remainder block from any remaining portion of the modified version of the variable length data block and the remaining portion of the at least one other variable length data block; and storing the remainder block in the remainder section (a new block is formed where the “remainder fits best,” C7 L33-45).
Regarding Claim 5, the cited prior art teaches the method of claim 1, wherein each variable length data block of the set has a maximum size of N * B, wherein N is an integer greater than or equal to two, and B is a maximum data size writable to the memory using a single memory access request (step 406 of Fig. 4, the full block corresponding to the maximum data size writable).
Regarding Claim 6, the cited prior art teaches the method of claim 5, wherein the portion of each variable length data block of the set stored in the chunk of memory allocated to that variable length data block comprises a first P non-overlapping portions of size B (these portions corresponding to the full size blocks of step 406 of Fig. 4), wherein P is a minimum of: (i) a number of non-overlapping portions of size B of the variable length data block, and (ii) X, wherein X is an integer less than N (a number of non-overlapping portions of size B are formed at step 406 of Fig. 4).
Regarding Claim 7, the cited prior art teaches the method of claim 6, wherein each of the M chunks of the memory allocated to the variable length data blocks in the set are equal-sized, and each of the M equal-sized chunks has a size of X*B (step 406 of Fig. 4, all the data blocks are equal-sized at X*B, where X=1).
Regarding Claim 8, the cited prior art teaches the method of claim 1, wherein the remaining portions of the variable length data blocks stored in the remainder section are stored adjacent to each other in the remainder section (C7 L33-45).
Regarding Claim 9, the cited prior art teaches the method of claim 8, wherein the remaining portions of the variable length data blocks in the set are stored adjacent to each other in the remainder section either starting from a starting address of the remainder section, or starting from a last address of the remainder section (shown on block 210 of Fig. 2b, C6 L23-35).
Regarding Claim 10, the cited prior art teaches the method of claim 5, wherein the remainder section is divided into a plurality of B- sized parts (the remainder section corresponding to the collection of B-sized parts that contain remainder data such as block 210 of Fig. 2b) and wherein the remaining portions of the variable length data blocks in the remainder section are stored by:
storing the remaining portion of a first variable length data block in the set at a start or at an end of the remainder section (step 408 of Fig. 4, also shown on block 210 of Fig. 2b);
making a determination, for each other variable length data block in the set, whether storing the remaining portion of the variable length data block adjacent to a previous remaining portion in the remainder section will cause the remaining portion of the variable length data block to be stored in at least two B-sized parts of the plurality of the B-sized parts (decision 410 of Fig. 4); in response to determining that storing the remaining portion of a variable length data block adjacent the previous remaining portion in the remainder section will cause the remaining portion to be stored in at least two B-sized parts of the plurality of the B-sized parts (“N” at step 410 of Fig. 4), storing the remaining portion at a start of a next B-sized part of the remainder section (step 414 of Fig. 4); and in response to determining that storing the remaining portion of a variable length data block adjacent to the previous remaining portion in the remainder section will not cause the remaining portion to be stored in at least two B-sized parts of the plurality of the B- sized parts (“Y” at step 410), storing the remaining porting adjacent the previous remaining portion in the remainder section (step 412 of Fig. 4, also see C7 L33-45).
Regarding Claim 11, the cited prior art teaches the method of claim 6, wherein the first P non-overlapping portions of size B of the variable length data blocks in the set are stored in the memory in an order (step 412 of Fig .7, C7 L53-59) and the remaining portions of the variable length data blocks in the set are stored in the remainder section in that same order or in a different order (C7 L33-45).
Regarding Claim 12, the cited prior art teaches the method of claim 6, wherein X is equal to N-1 (a number of non-overlapping portions of size B are formed at step 406 of Fig. 4, indicating N-1 portions of size B may be formed).
Regarding Claim 14, the cited prior art teaches the method of claim 1, further comprising storing, in a header section of the memory information indicating a size of each of the variable length data blocks in the set (header section indicating sizes of each of the variable length data block is shown on Fig. 2a).
Claim 16 is the memory system corresponding to the method of claim 1, and is rejected under similar rationale.
Claim 17 is the graphics processing system corresponding to the method of claim 1, and is rejected under similar rationale.
Claim 18 is the graphics processing system corresponding to the memory system of claim 16, and is rejected under similar rationale.
Claim 19 is the non-transitory computer readable storage medium corresponding to the method of claim 1, and is rejected under similar rationale.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Franaszek (US 5,761,536) in view of Bushman et al (US 9,626,249).
Regarding Claim 2, the cited prior art teaches the method of claim 1, but does not explicitly teach wherein the method further comprises determining whether the size of the remaining portion of the modified version of the variable length data block is the same or different from the size of the remaining portion of the corresponding variable length data block prior to the modification.
Bushman teaches determining whether the size of a portion of a modified version of the variable length data block is the same or different from the size of a portion of the corresponding variable length data block prior to the modification (“comparing the original size to the compressed [modified] size,” abstract).
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have implemented the determining of Bushman for the remaining portion of data of the cited prior art in order to determine whether to avoid compression.
Regarding Claim 3, the cited prior art teaches the method of claim 2, wherein it is determined that the size of the remaining portion of the modified version of the variable length data block is different (abstract of Bushman), and the method further comprises determining that there is at least one other remaining portion of the M variable length data blocks in the set that is affected by the size of the remaining portion of the modified variable length data block (the remaining portion of the modified version of the variable data length block is stored in a remainder section corresponding to the block which stores the “remainder of the line” along with the remaining portion of at least one other variable length data block, which is affected by having additional data stored in the same section of memory, C7 L33-45).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Franaszek (US 5,761,536) in view of Skinner et al (US 2016/0196804).
Regarding Claim 15, the cited prior art teaches the method of claim 1, but does not explicitly teach wherein each of the variable length data blocks represents a portion of frame buffer data.
Skinner teaches variable length data blocks representing a portion of frame buffer data (Paragraph 0115).
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have implemented the frame buffer of Skinner in the cited prior art in order to control display data.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Franaszek (US 5,761,536) in view of Rao et al (US 2019/0266307).
Regarding Claim 20, Franaszek teaches the memory system according to claim 16 as described in the rejection of claim 16 above, but does not explicitly teach a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a memory system that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the memory system.
Rao teaches non-transitory computer readable storage medium (Paragraph 0056) having stored thereon a computer readable dataset description of a memory system that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the memory system (“The system utilizes information derived from past experience designing, manufacturing and verifying circuit blocks to automatically provide circuit block descriptions and parameters from a storage source (e.g., database, distributed resource, memory, etc.). The system automatically generates a chip level list, including the instantiation of internal IC devices and connections between the circuit blocks for internal signals,” Paragraph 0105).
It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have implemented the non-transitory computer readable storage medium of Rao in the cited prior art in order to easily create an integrated circuit according to a given specification.
ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Claim Objections
Applicant's amendment with respect to the objection of claim 10 has been considered and have overcome the Examiner’s prior objections and thus are withdrawn.
Rejections – Double Patenting
Applicant’s terminal disclaimer filed 3/23/2026 has been approved, and thus the examiner’s prior double patenting rejections have been withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
On pages 9-10 of the submitted remarks, applicant argues “Franaszek does not appear to disclose storing a portion of the modified version of the variable length data block in the chunk of the memory allocated to the corresponding variable length data block in the set; and repacking any remaining portion of the modified version of the variable length data block in the remainder section along with the remaining portions of at least one other variable length data block in the set, as required by claim 1” for the following reasons:
Applicant argues “the "changed" cache line which needs to be saved to the main memory in Franaszek” is not the same thing as the claimed “modified version of the variable length data block of claim 1” because “the data that is stored is a modified version of a variable length data block among a set of M variable length data blocks stored in a memory. In other words, the data being stored is a modified version of a variable length data block that is already stored in the memory, e.g. which is read, modified and stored back in the allocated memory.”
This argument has been considered but is not persuasive.
On page 10 of the submitted remarks, applicant argues that “the data that is stored is a modified version of a variable length data block among a set of M variable length data blocks stored in a memory. In other words, the data being stored is a modified version of a variable length data block that is already stored in the memory, e.g. which is read, modified and stored back in the allocated memory.” This is not recited in the claims. The claim merely recites “storing a modified version of a variable length data block among a set of M variable length data blocks stored in a memory.” There is no indication the variable length data block is already stored in memory, merely that the modified version of a variable length data block is stored among M variable length data length blocks stored in a memory, which is taught by Franaszek as noted in the rejection above. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Further, even if the claims did recite that the variable length data block is already stored in the memory, this remains taught by the prior art, as Franaszek teaches the cache is used to temporarily store data from main memory (C4 L64-C5 L11). The data that is in the cache may be changed/modified (C7 L8-21). Therefore, data in the cache, which is eventually stored back to main memory, may be a modified version of the data already stored in memory.
Applicant argues on pages 10-11 of the submitted remarks that in the invention, “the modified version is stored back in the same allocated memory in which the pre-modified variable length data block was stored. Only the remainder section is required to be read and re-packed for the remainder of one or more of the other variable length data blocks of the set when one of the set is modified,” that data being stored in the invention is “a modified version of data that is already stored in the block(s) of memory in which the data is stored,” and that the changed/modified line is “stored in the same place as the original line” have been considered, but these limitations are not positively recited in the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
For these reasons, the examiner maintains the cited prior art teaches “storing a portion of the modified version of the variable length data block in the chunk of the memory allocated to the corresponding variable length data block in the set, and repacking any remaining portion of the modified version of the variable length data block in the remainder section along with the remaining portions of at least one other variable length data block in the set” as recited in claim 1.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Hansen (US 6,851,027) teaches a Memory System Organized Into Blocks Of Different Sizes And Allocation Method Therefor.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
SUBJECT MATTER CONSIDERED ALLOWABLE
Claim 13 contains allowable subject matter as indicated in the Non-Final Rejection mailed 12/23/2025, Page 15.
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-12 and 14-20 have been rejected in the application.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135
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