Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice for all Patent Application as subject to AIA
In the event the determination of the status of the application as subject to AIA
35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
RESPONSE TO REQUEST FOR CONTINUED EXAMINATION (RCE)
Amended claims 1-20 are pending and remain for further examination.
The New Grounds of Rejection
Applicant’s amendments and arguments with respect to claims 1-20 and request for continued examination (RCE) filed on May 26, 2026 have been fully considered, but they are deemed to be moot in view of the new grounds of rejections. Applicant’s amendment necessitated the new modified rejections.
Claim Rejections - 35 USC § 103
The text of those sections of title AIA 35 U.S.C. 103 code not included in this action can be found in a prior Office Action.
Claims 1-20 are rejected under AIA 35 U.S.C. 103 as being un-patentable over Johnson (U.S. Patent No. 10,001,933 B2) in view of Pan et al (U.S. Patent Application Publication No. 2017/0293451 A1).
As to claim 1, Johnson discloses a network adapter (see figures 1-2, column 3 line 60 to column 4 line 4), comprising: a plurality of network-adapter cores, to serve at least a host in transmitting and receiving packets over a packet network, wherein each of the network-adapter cores is to serve the host as a respective network adapter independently of other network-adapter cores and identify itself to the host as a respective different network adapter (figures 1-2, column 6 lines 33-42, column 10 line 30 to column 11 line 6, column 30 lines 6-35, I/O adapter having the processor cores are processing data independently on behalf of the host processor); a host interface, to connect the plurality of network-adapter cores to the host (figures 1-2, column 3 line 60 to column 4 line 4, column 4 lines 30-41, a host device and an adapter device / processor cores communicate through a host interface); and a network interface, to connect the plurality of network-adapter cores to the packet network via port (figure 2, column 11 lines 31-54).
However, Johnson does not disclose a crossbar circuit, to connect the plurality of network-adapter cores to the packet network via multiple port circuits.
Pan et al disclose a network adapter (see figures 1-3), comprising: a crossbar circuit, to connect the plurality of network-adapter cores to the packet network via multiple port circuits (figure 1, pars. 0023 & 0028, figures 2-3, pars. 0031-0032).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate the teaching of Pan et al as stated above with the network adapter of Johnson for connecting the plurality of cores with the plurality of ports for transmitting and receiving packets over the packet network because it would have improved the processing speed of transmit/receive the data packet and also improved the network adapter utilization for transmit/receive the data packet.
As to claim 2, Pan et al disclose that a network-adapter core is to select a port circuit for transmitting a packet to the network by applying a criterion aiming to balance a traffic load among the multiple port circuits (figures 1-3, pars. 0023, 0028, 0031-0035, figure 4B, pars. 0044 & 0046).
As to claims 3-4, Pan et al disclose that two or more of the network-adapter cores are to queue packet descriptors, of packets that are destined to a port circuit, in respective queues associated with the port circuit; and the port circuit is to pop the packet descriptors from the queues of the network-adapter cores in accordance with a scheduling criterion, and to send the corresponding packets to the packet network, wherein the scheduling criterion aims to apply fairness among a subset of the queues of the network-adapter cores that are non-empty (figures 1-3, pars. 0023, 0028, 0031-0035, figure 9, pars. 0059-0063).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate the teaching of Pan et al as stated above with the network adapter of Johnson for connecting the plurality of cores with the plurality of ports for transmitting and receiving packets over the packet network because it would have improved the processing speed of transmit/receive the data packet and also improved the network adapter utilization for transmit/receive the data packet.
As to claims 5-7, Johnson discloses that a port circuit is to receive packets from the packet network and, for each packet, to determine a network-adapter core that will process the packet, and to send the packet to the determined network-adapter core, the port circuit is to determine the network-adapter core depending on a destination address specified in the packet and also based on a value specified in the packet header (figures 1-3, column 6 lines 22-63, column 10 lines 8-29, column 11 lines 31-54, and column 16 lines 17-49).
As to claims 8-9, Johnson discloses that the host comprises one or more hosts, the host interface is to communicate with the one or more hosts over a peripheral bus, and is configurable to set-up multiple links of the peripheral bus, connecting each network-adapter core to one or more of the hosts. the host interface is to assign each of the network-adapter cores one or more unique physical functions of the peripheral bus (figure 2, column 11 lines 31-54).
As to claim 10, Pan et al disclose that any of the network-adapter cores is to communicate packets with any of the port circuits; any of the port circuits is to communicate packets with any of the network-adapter cores; and the crossbar circuit is to connect any of the network- adapter cores with any of the port circuits (figures 1-3, pars. 0023, 0028, 0031-0035, figure 9, pars. 0059-0063).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate the teaching of Pan et al as stated above with the network adapter of Johnson for connecting the plurality of cores with the plurality of ports for transmitting and receiving packets over the packet network because it would have improved the processing speed of transmit/receive the data packet and also improved the network adapter utilization for transmit/receive the data packet.
As to claims 11-20, they are also rejected for the same reasons set forth to rejecting claims 1-10 above, since claims 11-20 are merely method of operations for the apparatus defined for the claims 1-10, and claims 11-20 do not teach or define any new limitations than above rejected claims 1-10.
Response to Arguments
Applicant’s amendments with respect to the claims 1-20 filed on May 26, 2026 have been fully considered but they are deemed to be moot in a new ground(s) of rejection is made in view of new references. The examiner has attempted to answer (response) to the remarks (arguments) in the body of the Office Action (see new modified/updated rejection of the amended claims).
Additional Reference
The examiner as of general interest cites the following reference.
Cosby et al, U.S. Patent No. 11,755,438 B2.
Content Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bharat Barot whose telephone number is (571)272-3979. The examiner can normally be reached on 7:00AM-3:30PM.
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/BHARAT BAROT/Primary Examiner, Art Unit 2453July 17, 2026
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