DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of claims 10 and 20 must be shown or the feature(s) canceled from the claim(s). Currently, claim 10 recites “a first resistor having a first terminal coupled to the first current output, and a second terminal; a second resistor having a first terminal coupled to the second current output, and a second terminal; a sample and hold circuit having an input coupled to the second terminal of the first resistor and the second terminal of the second resistor”, however, Figure 2 shows that the same and hold circuit has an input coupled to the first terminals of the respective first and second resistors. Claim 20 claims a third current at the second current output but nothing like that is shown in the Figures. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0007 recites “FIG. 2 is schematic” which should be changed to “FIG. 2 is a schematic”.
Paragraph 0015 recites “FIG. 2 is schematic” which should be changed to “FIG. 2 is a schematic”.
Paragraph 0014 recites “turn-of” which should be changed to “turn-off”.
Paragraph 0015 recites “second output the voltage” which should be changed to “second outputs of the voltage”
Paragraph 0019 recites “some examples of the 108” which should be changed to “some examples of the slew rate detection circuit 108”.
Appropriate correction is required.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Resistor Based Slew Rate Detection Circuit”.
Claim Objections
Claims 4, 7, 18 and 20 are objected to because of the following informalities:
Claim 4, line 1, change “wherein”” to “wherein”.
Claim 4, line 5, change “and second control” to “and a second control”.
Claim 7, line 1, change “includes”” to “includes”.
Claim 10 recites “a first resistor having a first terminal coupled to the first current output, and a second terminal; a second resistor having a first terminal coupled to the second current output, and a second terminal; a sample and hold circuit having an input coupled to the second terminal of the first resistor and the second terminal of the second resistor”. However, based on the specification this limitation should be changed to “a first resistor having a first terminal coupled to the first current output, and a second terminal; a second resistor having a first terminal coupled to the second current output, and a second terminal; a sample and hold circuit having an input coupled to the first terminal of the first resistor and the first terminal of the second resistor”.
Claim 18, lines 2-3, change “provide a second slew” to “provide the second slew”.
Claim 20, line 5, change “and’” to “and”.
Appropriate correction is required.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Masaoka (US 2016/0072501 A1) in view of Spillane (US 2024/0120823 A1).
Regarding claim 1, Masaoka teaches a circuit (Figure 7) comprising: a current source (Figure 7 Component 161+162A+162B+162C) having a first current input (Figure 7 Component 161 receives a current input) coupled to an input terminal (Figure 7 Component 161 bottom terminal is coupled to IREF which is the input terminal), a first current output (Figure 7 Component 162A output), and a second current output (Figure 7 Component 162B output); a first switch (Figure 7 Component 163A) having a first terminal coupled to the first current output (Figure 7 Component 163A top terminal), and a second terminal (Figure 7 Component 163A bottom terminal); a second switch (Figure 7 Component 163B) having a first terminal coupled to the second current output (Figure 7 Component 163B top terminal), and a second terminal (Figure 7 Component 163B bottom terminal); a sample and hold circuit having an input coupled to the second terminal of the first switch and the second terminal of the second switch (Figure 7 Component 144), and an output (Figure 7 Component 144 output VTS); and an analog-to-digital converter (ADC) having an input coupled to the output of the sample and hold circuit (Figure 7 Component 150S is a digital comparator that outputs 1 or 0 thus constituting it as a one-bit analog-to-digital converter because it compares the analog voltage VTS with reference voltage VTRS and produces a binary digital comparison signal SCS).
Masaoka does not teach a first current input coupled to an input terminal configured for resistor connection.
Spillane teaches a circuit (Figure 3), comprising: a current source (Figure 3 Component 310) having a first current input (Figure 3 Component I_ILIM) coupled to an input terminal configured for resistor connection (Figure 3 Component ILIM is the input terminal configured to Component Resistor at node cscomp).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Masaoka and configure the IRFE input of the current mirror using the resistor programmed current input taught by Spillane. The advantage of this design is that it would provide external calibration of the capacitor charging rate and corresponding VTS range for different desired transistor times or operating conditions.
Regarding claim 4, Masaoka and Spillane teach all the limitations of claim 1. Masaoka further teaches wherein the first switch has a first control input (Figure 7 Component 163A receives signal SAS at the control input of Component 163A), and the second switch has a second control input (Figure 7 Component 163B receives signal SAS at the control input of Component 163B); and the circuit includes a control circuit (Paragraph 0152 “the control device 210 generates the rising regulating signal SAS”) having a first control output coupled to the first control input, and second control output coupled to the second control input (Paragraph 0154 “In a case where the electric current quantity (small) is selected, the control device 210 generates the rising regulating signal SAS which turns the regulation switch 163A ON and turns the regulation switch 163B and the regulation switch 163C OFF”).
Regarding claim 5, Masaoka and Spillane teach all the limitations of claim 4. Masaoka further teaches wherein: the control circuit is configured to: provide a first switch control pulse at the first control output to close the first switch (Paragraph 0152 “In a case where the electric current quantity (small) is selected, the control device 210 generates the rising regulating signal SAS which turns the regulation switch 163A ON and turns the regulation switch 163B and the regulation switch 163C OFF”), and provide a second switch control pulse at the second control output to close the second switch (Paragraph 0156 “In a case where the electric current quantity (middle) is selected, the control device 210 generates the rising regulating signal SAS which turns the regulation switch 163A and the regulation switch 163B ON”); and the first switch control pulse precedes the second switch control pulse (Paragraphs 0154-0161 show that the first switch control pulse preceded the second switch control pulse).
Regarding claim 7, Masaoka and Spillane teach all the limitations of claim 1. Masaoka further teaches wherein the current source (Figure 7 Components 161+162A+162B+162C) includes a first transistor (Figure 7 Component 161) having a first terminal (Figure 7 Component 161 top terminal), a second terminal coupled to the input terminal (Figure 7 Component 161 bottom terminal), and a control terminal (Figure 7 Component 161 gate terminal) coupled to the second terminal of the first transistor (Figure 7 Component 161 gate terminal is coupled to the bottom terminal of Component 161); a second transistor (Figure 7 Component 162A) having a first terminal coupled to the first terminal of the first transistor (Figure 7 Component 162A top terminal is coupled to the top terminal of Component 161), a second terminal coupled to the first terminal of the first switch (Figure 7 Component 162A bottom terminal is coupled to the top terminal of Component 163A), and a control terminal coupled to the control terminal of the first transistor (Figure 7 Component 163A gate terminal is coupled to the gate terminal of Component 161); and a third transistor (Figure 7 Component 162B) having a first terminal coupled to the first terminal of the first transistor (Figure 7 Component 162B top terminal is coupled to the top terminal of Component 161), a second terminal coupled to the first terminal of the second switch (Figure 7 Component 162B bottom terminal is coupled to the top terminal of Component 163B), and a control terminal coupled to the control terminal of the first transistor (Figure 7 Component 162B gate terminal is coupled to the gate terminal of Component 161).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Masaoka (US 2016/0072501 A1) in view of Spillane (US 2024/0120823 A1) and in further view of Abesingha (US 2023/0396141 A1).
Regarding claim 2, Masaoka and Spillane teach all the limitations of claim 1. Masaoka does not teach a resistor coupled between the first terminal of the first switch and a reference terminal.
Abesingha teaches a circuit (Figure 6), comprising: a first current output (Figure 6 Component Ihs), and a second current output (Figure 6 Component Ils); a first switch (Figure 6 Component SWΔths) having a first terminal coupled to the first current output (Figure 6 Component SWΔths left terminal), and a second terminal (Figure 6 Component SWΔths right terminal); a second switch (Figure 6 Component SWΔtls) having a first terminal coupled to the second current output (Figure 6 Component SWΔtls left terminal), and a second terminal (Figure 6 Component SWΔtls right terminal); a sample and hold circuit (Figure 6 Component 635; Paragraph 0060 “sample and hold (e.g., via block 635) of the voltage-converted”) having an input coupled to the second terminal of the first switch and the second terminal of the second switch (Figure 6 Component 635 has an input coupled to the right terminals of Components SWΔths and SWΔtls), and an output (Figure 6 Component 635 output); an analog-to-digital converter (ADC) having an input coupled to the output of the sample and hold circuit (Paragraph 0068 highlights that an ADC can be added at the output of the capacitor in the sample and hold circuit); a resistor coupled between the first terminal of the first switch and a reference terminal (Figure 6 Component Rhs); and a resistor coupled between the first terminal of the second switch and the reference terminal (Figure 6 Component Rls).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Masaoka and providing resistors between the current mirrors and the output going to the sample and hold circuit as taught by Abesingha. The advantage of this design is it would convert each mirrored output current into a defined voltage before selective sampling (Abesingha Paragraph 0060 and 0057) which would allow for independent scaling of the two current derived voltage and improve measurement accuracy.
Regarding claim 3, Masaoka and Spillane teach all the limitations of claim 1. Masaoka does not teach teaches a resistor coupled between the first terminal of the second switch and a reference terminal.
Abesingha teaches a circuit (Figure 6), comprising: a first current output (Figure 6 Component Ihs), and a second current output (Figure 6 Component Ils); a first switch (Figure 6 Component SWΔths) having a first terminal coupled to the first current output (Figure 6 Component SWΔths left terminal), and a second terminal (Figure 6 Component SWΔths right terminal); a second switch (Figure 6 Component SWΔtls) having a first terminal coupled to the second current output (Figure 6 Component SWΔtls left terminal), and a second terminal (Figure 6 Component SWΔtls right terminal); a sample and hold circuit (Figure 6 Component 635; Paragraph 0060 “sample and hold (e.g., via block 635) of the voltage-converted”) having an input coupled to the second terminal of the first switch and the second terminal of the second switch (Figure 6 Component 635 has an input coupled to the right terminals of Components SWΔths and SWΔtls), and an output (Figure 6 Component 635 output); an analog-to-digital converter (ADC) having an input coupled to the output of the sample and hold circuit (Paragraph 0068 highlights that an ADC can be added at the output of the capacitor in the sample and hold circuit); a resistor coupled between the first terminal of the first switch and a reference terminal (Figure 6 Component Rhs); and a resistor coupled between the first terminal of the second switch and the reference terminal (Figure 6 Component Rls).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Masaoka and providing resistors between the current mirrors and the output going to the sample and hold circuit as taught by Abesingha. The advantage of this design is it would convert each mirrored output current into a defined voltage before selective sampling (Abesingha Paragraph 0060 and 0057) which would allow for independent scaling of the two current derived voltage and improve measurement accuracy.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the ADC is configured to: provide a first value representative of current flow through a first resistor and a second resistor coupled to the input terminal responsive to the first switch control pulse; and provide a second value representative of current flow through the first resistor responsive to the second switch control pulse.
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 8, Nishimura (US 2024/0106424 A1) teaches a circuit (Figure 1) comprising: a transistor (Figure 1 Component LS) having a control terminal (Figure 1 Component LS gate terminal); a driver circuit (Figure 1 Component 106 is seen in further detail in Figure 2B; Figure 2B Component 203B) having an output coupled to the control terminal (Figure 2B Component 203B output signal IADJDRV), and a slew control input (Figure 2B Component 203B input signal IADJ); a slew rate detection circuit (Figure 2B Component 202B) having a slew control output coupled to the slew control input (Figure 2B Component 202B output signal IADJ), and a slew setting terminal (Figure 2B Component 204B Gate Terminal), the slew rate detection circuit configured to: determine a first slew rate based on a first current at the slew setting terminal, and provide a first slew rate control signal, representing the first slew rate, at the slew control output (Figure 2B Component 202B; Paragraphs 0035 and 0037-0039)
However, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the slew rate detection circuit is configured to determine a second slew rate based on a second current at the slew setting terminal, and provide a second slew rate control signal, representing the second slew rate, at the slew control output.
Claims 9-14 are dependent upon claim 8 and are therefore also allowed.
Regarding claim 15, Nishimura (US 2024/0106424 A1) teaches a switch-mode converter (Figure 1) comprising: a transistor (Figure 1 Component LS) having a control terminal (Figure 1 Component LS gate terminal); a control circuit (Figure 1 Component 106 is seen in further detail in Figure 2B; Figure 2B Component 200B) having a slew setting terminal (Figure 2B Component SN), the control circuit including: a driver circuit (Figure 1 Component 106 is seen in further detail in Figure 2B; Figure 2B Component 203B) having an output coupled to the control terminal (Figure 2B Component 203B output signal IADJDRV), and a slew control input (Figure 2B Component 203B input signal IADJ); a slew rate detection circuit (Figure 2B Component 202B) having a slew control output coupled to the slew control input (Figure 2B Component 202B output signal IADJ), and an input coupled to the slew setting terminal (Figure 2B Component 202B has an input, through Component Cfb, coupled to Component SN), the slew rate detection circuit configured to: determine a first slew rate based on a first current at the slew setting terminal, and provide a first slew rate control signal, representing the first slew rate, at the slew control output (Figure 2B Component 202B; Paragraphs 0035 and 0037-0039).
However, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests the slew rate detection circuit configured to determine a second slew rate based on a second current at the slew setting terminal, and provide a second slew rate control signal, representing the second slew rate, at the slew control output
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 16-20 depend upon claim 15 therefore are also allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
D’Souza (US 2024/0128852 A1) teaches a high-side gate driver driving a high-side switch of a switching converter determines a first transition between a first sub-duration and a second sub-duration as being when a voltage at the switching node (of the high-side switch) becomes less than a voltage at the power terminal by a first threshold voltage. The gate driver determines a second transition between the second sub-duration and a third sub-duration as being when a voltage of the control signal crosses a threshold voltage of the high-side switch. In an embodiment, the second sub-duration corresponds to Miller Plateau.
Lee (US 2021/0126636 A1) teaches a circuit that includes a transistor control circuit having an input and an output adapted to be coupled to the output of the transistor control circuit and can provide a slew-rate compensation voltage proportional to a slew-rate of a control voltage of the transistor. A reference voltage source can be coupled to the slew-rate compensator to provide a reference voltage at the output of the reference voltage source, the slew-rate compensator configured to add the slew-rate compensation voltage to the reference voltage to provide an adjusted reference voltage at the output of the slew rate compensator. A reference comparator having a first input, a second input and an output is coupled to the input of the transistor control circuit. The first input can be coupled to the control terminal of the transistor, and the second input can be coupled to the output of the slew-rate compensator.
Rueger (US 2013/0113524 A1) teaches an output buffer that includes a pullup driver, a pulldown driver, and an output stage. The pullup driver has a drive control input, and an output for providing a pullup drive signal in a push-pull mode in response to receiving a first drive control signal on the drive control input, and in a current limited mode in response to receiving a second drive control signal on said drive control input. The pulldown driver has a drive control input, and an output for providing a pulldown drive signal in the push-pull mode in response to receiving a third drive control signal on the drive control input, and in the current limited mode in response to receiving a fourth drive control signal on the drive control input. The output stage provides a voltage on an output terminal in response to the pullup and pulldown drive signals.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Shahzeb K Ahmad/Examiner, Art Unit 2838
Prosecution Insights