DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/14/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1 “requesting, by a control logic, to the issue queue, to complete the first operation”. While Fig. 7 shows the variable latency execution engine sending a request to the issue queue, control logic 556 is shown to be separate from the execution engines in Fig. 5. The figures do not show control logic sending the request to the issue queue.
Claim 5 “delivering the result of the first operation to an entry of the issue queue occupied by a depending operation”. While Fig. 7 shows delivering the variable latency operation result to a dependent operation pipeline, the dependent operation pipeline is shown to be separate from the issue queue. The figures do not show an entry of the issue queue occupied by a depending operation that the result is delivered to.
Claim 6 “where the delivering is accomplished by a bypass path in the common write-back pipeline”
Fig. 7 is further objected to under 37 CFR 1.84(p)(3) because it includes text on shaded surfaces.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“requesting, by a control logic… to complete the first operation” in claim 1
“requesting, by a control logic… to complete the first operation” in claim 19
“request, by a control logic… to complete the first operation” in claim 20
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. However, since the specification does not disclose the specific structure of the control logic for performing the claimed function, a 112(a)/(b) rejection appears below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claims 1, 7, 17, and 19-20 are objected to because of the following informalities:
Claim 1 recites “when the first operation finishes execution” in lines 11-12, however the claim never introduces execution of the first operation. Examiner suggests introducing execution of the first operation to improve clarity.
claims 19 and 20 recite the same limitation and are objected to for the same reasons.
Claim 7 line 1- “results” should be --result-- to be consistent with how the term is introduced in claim 1
Claim 17 recites “the execution of the variable latency operation”, however, the claim never introduces execution of the variable latency operation. Examiner suggests introducing execution of the variable latency operation to improve clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “requesting, by control logic… to complete the first operation” in line 11. Since this limitation invokes 112(f), the specification is required to disclose the specific structure for performing this function. While the specification at [0052] discloses a control logic 556 (shown in Fig. 5) that makes a request to complete a variable latency operation, the specification does not disclose the specific structure of the control logic for performing this function.
Claims 19-20 recite the same limitation and are rejected for the same reasons. Claims 2-18 are rejected based on their dependence from claim 1.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The rejections corresponding to the 112(f) invocations appear first.
Claim 1 limitation “requesting, by control logic… to complete the first operation” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. While the specification at [0052] discloses a control logic 556 (shown in Fig. 5) that makes a request to complete a variable latency operation, the specification does not disclose the specific structure of the control logic for performing this function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Claims 19-20 recite the same limitation and are rejected for the same reasons. Claims 2-18 are rejected based on their dependence from claim 1.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim 4 recites “wherein the execution stage is a second execution stage”. It is unclear in what sense the execution stage is a “second” execution stage since the claim does not introduce a first execution stage. For purposes of examination, this limitation will be interpreted as a second execution stage of two execution stages.
Claim 5 recites “delivering the result of the first operation to an entry of the issue queue occupied by a depending operation” in lines 1-2. However, the specification at [0059] describes “Bypass logic 750 can include one or more registers 752 and multiplexors which can make the result from the variable latency operation available to the depending fixed latency operation in the third intermediate execution stage (E3 715) of the fixed latency execution engine pipeline.” which indicates that the result of the first operation is delivered to the depending operation in an execution stage and not in an entry of the issue queue (Fig. 7 shows the issue queue separate from execution stage E3 where the result is delivered to). Thus, while this limitation may be clear taken at face-value, it is rendered indefinite because it is inconsistent with the specification. See MPEP 2173.03. For purposes of examination, this limitation will be interpreted as recited.
Claim 13 recites “the requesting [includes] a second variable latency operation”. It is unclear how the requesting to complete the first operation described in claim 1 includes a second variable latency operation- does the requesting to complete the first operation include performing a second variable latency operation or does this limitation mean requesting to complete a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim 13 recites “the arbitrating [includes] a second variable latency operation”. It is unclear how the arbitrating for an opening described in claim 1 includes a second variable latency operation- does the arbitrating for the opening include performing a second variable latency operation or does this limitation mean arbitrating for an opening for a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim 13 recites “the granting [includes] a second variable latency operation”. It is unclear how the granting to complete the first operation described in claim 1 includes a second variable latency operation- does the granting to complete the first operation include completing a second variable latency operation or does this limitation mean granting to complete a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim 13 recites “the completing [includes] a second variable latency operation”. It is unclear how the completing the first operation described in claim 1 includes a second variable latency operation- does completing the first operation include completing a second variable latency operation or does this limitation mean completing a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claims dependent from a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-11, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Olson US 2013/0179664 in view of Brooks US 7,373,489.
Regarding claim 1, Olson teaches:
1. A processor-implemented method for instruction execution comprising:
accessing a processor core (Fig. 2 core 100), wherein the processor core supports variable latency operations ([0079]: the FGU executes operations in a variable number of cycles (i.e., supports variable latency operations)), wherein the processor core includes an execution pipeline (Fig. 2, 240-255 are an execution pipeline), wherein the execution pipeline is coupled to an issue queue (Fig. 2 and 7: scheduler unit 225, issue unit 230, and arbitration unit 710 are an issue queue, see also Fig. 8 showing an instruction queue in the scheduler unit), and wherein the issue queue is coupled to a common write-back pipeline ([0079] describes that the units of Fig. 2 may be implemented as pipeline stages to form a pipeline that ends with result commitment, the stages of the pipeline corresponding to the execution units 235-255 to the result commitment are a common write-back pipeline);
issuing, by the issue queue, a first operation to a first execution engine within the execution pipeline, wherein the first operation is a variable latency operation ([0050]: the issue unit issues instructions to FGU 255 (which may include a variable latency operation, see [0079]), and the FGU includes a divide engine 310, see [0082], which is a first execution engine that may execute the operation);
issuing, by the issue queue, one or more additional operations to one or more additional execution engines in the execution pipeline, wherein at least one of the one or more additional operations is a fixed latency operation ([0050]: the issue unit issues instructions to EXU1, i.e., one or more additional execution engines));
requesting, by a control logic, to the issue queue, to complete the first operation, when the first operation finishes execution within the first execution engine ([0128] and [0136]: control unit 910 in the divide engine 310 requests to the arbitration unit 710 to pass its results along (i.e., to complete the first operation) when it has produced the result (i.e., when the operation finishes execution within the engine));
arbitrating, by the issue queue, for an opening, wherein the opening is in the common write-back pipeline ([0128]: the arbitration unit arbitrates among multiple received requests from the divide engines by selecting a request to grant (which may include waiting for the post-engine to become available before selecting a request to grant) and requesting a bubble in the pipeline for the request, selecting (or waiting and then selecting) a request arbitrates among the multiple requests for the bubble/opening that the arbitration unit requests, and the opening is used to commit results by inserting the final quotient back into the instruction pipeline, see [0125] and [0132], which indicates that the opening is in the common write-back pipeline);
granting, by the issue queue, to complete the first operation, wherein the granting is based on the arbitrating (by granting the request to the engine, see [0128], and inserting a bubble for the final quotient (based on arbitrating for the bubble), see [0063] and [0125], the issue queue grants to complete the first operation based on the arbitrating); and
completing the first operation, wherein the completing includes inserting, at the opening in the common write-back pipeline, a result of the first operation ([0125] and [0132]: the final quotient (i.e., a result of the first operation) is inserted at the bubble/opening to commit the results, which completes the operation).
Olson does not explicitly teach fixed latency operations or the additional operations being fixed latency operations.
However, Brooks teaches fixed latency operations (col 1 lines 16-17 discloses integer instructions that are configured to execute in an integer pipeline of a particular depth, which are fixed latency operations)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the integer instructions of Olson (see [0065]) to execute in a pipeline/execution unit of a particular depth as taught by Brooks such that the integer instructions of the combination would be fixed latency operations. One of ordinary skill in the art would have been motivated to make this modification to improve scheduling of the instructions since fixed latency instructions with known execution times can be scheduled more efficiently than variable latency instructions.
Claim 19 is directed to a non-transitory computer readable medium storing code that generates logic for performing the method of claim 1 and is rejected for the same reasons as claim 1.
Claim 20 is directed to a computer system comprising one or more processors executing instructions stored on memory to perform the method of claim 1 and is rejected for the same reasons as claim 1, see also Olson [0024] disclosing memory storing executable instructions.
Regarding claim 2, Olson in view of Brooks teaches:
2. The method of claim 1 wherein the arbitrating comprises halting, by the issue queue, a pick stage for a second operation within the one or more additional operations (Olson [0132] describes the pick logic/stage inserting pipeline stalls, which stalls the pick stage for instructions in the instruction queue (as the pick stage would otherwise pick the instructions from the instruction queue, see also Fig. 8), which includes a second operation within the one or more additional operations as the instruction queue stores instructions other than divide instructions, see [0131]).
Regarding claim 3, Olson in view of Brooks teaches:
3. The method of claim 2 wherein the inserting occurs at an execution stage of the common write-back pipeline (Olson [0128]: the request to insert a bubble is submitted based on the request from the engine 310, i.e., at an execution stage of the pipeline corresponding to engine 310).
Regarding claim 4, Olson in view of Brooks teaches:
4. The method of claim 3 wherein the execution stage is a second execution stage (Olson Fig. 7 shows the divide engines 310 at a second execution stage after the stage corresponding to divide pre-engine 320).
Regarding claim 9, Olson in view of Brooks teaches:
9. The method of claim 1 wherein the arbitrating comprises stalling, by the issue queue, the first operation (Olson [0128]: if the post-engine is not available, the arbitration unit arbitrates among multiple requests from the divide engines by stalling the divide engines until the post-engine is available, which stalls the first operation at the engine, and then selecting one of the requests once it becomes available).
Regarding claim 10, Olson in view of Brooks teaches:
10. The method of claim 1 further comprising completing the one or more additional operations (Olson [0078]-[0079]: TLU 275 completes instructions, including the instructions executed by EXU1 (i.e., the one or more additional operations) at the end of the instruction pipeline).
Regarding claim 11, Olson in view of Brooks teaches:
11. The method of claim 1 wherein the processor core includes one or more additional execution pipelines (Olson Fig. 1, EXU0 235 is an additional execution pipeline).
Regarding claim 13, Olson in view of Brooks teaches:
13. The method of claim 1 wherein the requesting, the arbitrating, the granting, and the completing include a second variable latency operation (Olson since FGU 255 processes variable latency operations, see [0079], and the issue unit issues instructions to FGU 255, see [0050], the issue unit may issue a second variable latency instruction for which arbitrating, granting, and completing may be performed for).
Regarding claim 14, Olson in view of Brooks teaches:
14. The method of claim 1 wherein the variable latency operation is identified by the issue queue (Olson [0050]: the issue unit identifies instructions, including variable latency operations executed by the FGU, in order to issue them to the appropriate execution unit, see also [0062] disclosing that the instruction queue in the scheduler stores decoded instructions, which would also identify a variable latency operation by decoding it).
Regarding claim 15, Olson in view of Brooks teaches:
15. The method of claim 1
While Olson teaches executing a floating-point square root operation in a divide unit, see [0027], which is in the FGU 255 which executes certain types of operations in a variable number of cycles, see [0079] and [0082], Olson does not explicitly teach the floating-point square root operation being a variable latency operation.
However, Brooks further teaches square-root instruction that is a variable latency operation (col 12 lines 35-37: square-root instructions may execute in a variable number of cycles).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the floating-point square root operation of Olson to be a variable latency operation as taught by Brooks. One of ordinary skill in the art would have been motivated to make this modification to reduce timing constraints and allow more flexibility in how the floating-point square root operation is executed.
Regarding claim 16, Olson in view of Brooks teaches:
16. The method of claim 1
While Olson teaches executing a floating-point divide operation in a divide unit, see [0027], which is in the FGU 255 which executes certain types of operations in a variable number of cycles, see [0079] and [0082], Olson does not teach explicitly teach the floating-point divide operation being a variable latency operation.
However, Brooks further teaches a divide operation that is a variable latency operation (col 12 lines 35-37: divide instructions may execute in a variable number of cycles).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the floating-point divide operation of Olson to be a variable latency operation as taught by Brooks. One of ordinary skill in the art would have been motivated to make this modification to reduce timing constraints and allow more flexibility in how the floating-point divide operation is executed.
Regarding claim 17, Olson in view of Brooks teaches:
17. The method of claim 1 wherein the execution of the variable latency operation is not pipelined (Olson [0070]: instructions implemented by the FGU may block issue until complete, i.e., the execution of the instructions is not pipelined).
Regarding claim 18, Olson in view of Brooks teaches:
18. The method of claim 1 wherein the processor core executes one or more instructions out of order (Olson [0027]: each core executes instructions out of order).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Olson US 2013/0179664 in view of Brooks US 7,373,489 and Colwell US 6,101,597.
Regarding claim 5, Olson in view of Brooks teaches:
5. The method of claim 3 further comprising delivering the result of the first operation to the issue queue for a depending operation, wherein the depending operation includes a dependency on the result of the first operation ([0064]: the issue unit may read source operands of dependent instructions directly from the result bus).
Olson in view of Brooks does not teach delivering the result to an entry of the issue queue occupied by a depending operation
However, Colwell teaches that a result may provide/deliver an input operand to waiting instructions buffered in the reservation station to indicate that the source operand is ready for dispatch along with instructions using the operand, see col 3 lines 56-61.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Olson to deliver the source operand of a dependent instruction (i.e., the result of the first operation) to an entry occupied by the dependent instruction as taught by Colwell. One of ordinary skill in the art would have been motivated to make this modification to enable faster dispatch of dependent instructions with their source operands once the source operands are ready.
Regarding claim 6, Olson in view of Brooks and Colwell teaches:
6. The method of claim 5 wherein the delivering is accomplished by a bypass path in the common write-back pipeline (Olson [0064] discloses that the source operand may be bypassed directly from the execution unit result bus, the path used for the bypassing is a bypass path in the common write-back pipeline).
Regarding claim 7, Olson in view of Brooks and Colwell teaches:
7. The method of claim 5 further comprising writing the results of the first operation, in a writeback stage of the common write-back pipeline, to a register file (Olsen [0064] discloses that the results may be sourced from register files indicating the architectural state and [0078]-[0079] discloses committing working results to the architectural state, which indicates that the results are written to a register file and the corresponding stage is a writeback stage of the common write-back pipeline).
Regarding claim 8, Olson in view of Brooks and Colwell teaches:
8. The method of claim 7 further comprising reading, from the register file, the results of the first operation (Olson [0064]: the results are sourced from/read from the register file).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Olson US 2013/0179664 in view of Brooks US 7,373,489 and Kahle US 6,728,866.
Regarding claim 12, Olson in view of Brooks teaches:
12. The method of claim 11
Olson in view of Brooks does not teach:
wherein each execution pipeline in the one or more additional execution pipelines includes a unique issue queue.
However, Kahle teaches a unique issue queue for each functional unit, see col 7 lines 54-59 and Fig. 3. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Olson to include a unique issue queue for the execution units as taught by Kahle such that EXU0 of the combination would include a unique issue queue. One of ordinary skill in the art would have been motivated to make this modification to issue instructions without the delay associated with determining which execution unit to choose (Kahle col 7 lines 62-65).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,478,225 teaches a fetch unit that inserts a bubble into the pipeline to guarantee that a longer latency instruction will not conflict with a shorter latency instruction, see Fig. 7
US 6,704,822 teaches an arbitration circuit that arbitrates access to a shared resource such as a writeback buffer when a collision is detected from two processing units by preferring one MPU and causing the other to retry its access, see Fig. 8 and corresponding description
US 10,915,359 teaches preventing conflicts between a low latency and high latency pipeline by scheduling execution based on the number of cycles the execution requests take to complete, see Fig. 5 and corresponding description
US 2010/0306510 teaches bypass circuits that detect dependency conditions and arbitrate access to instruction results so that dependent instructions can be executed without having to wait for the results to be written to the register file, see [0079]
US 2024/0078035 teaches a write-back reschedule circuit that stalls an execution unit prior to its write-back stage and then monitors upcoming operations to identify whether to forward results from the execution unit or to write the results to the registers, which may simplify forwarding logic between the execution units and registers, see [0027]-[0030]
US 5,604,878 teaches adding delay stages to an execution unit pipeline when it will conflict with the writeback of another execution unit, see Abstract
US 2002/0169944 teaches short and long latency threads connected by a multiplexor to a common write bus to the register file, where the short latency thread has priority and the long latency threads contain a result buffer to avoid conflicts, see [0060]
US 2022/0035637 teaches an issue queue that uses a result buffer to delay an instruction when it determines a collision will occur with another instruction, see Abstract
US 2019/0243646 teaches storing a ready value indicating whether the result of a variable latency instruction is ready in a dedicated writeback queue, see Abstract and [0096]
US 2019/0370004 teaches issue circuitry that delays an instruction by adding an execution stage to its pipeline to avoid a conflict at the write port, see Abstract
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/KASIM ALLI/Examiner, Art Unit 2183 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183