DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 06/15/2026. Claims 1, 3, and 5-20 are pending. Claims 1, 3, 7, 13, and 19-20 are amended. Claims 2 and 4 are canceled.
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
On page 7 of the Remarks, Applicant argues, with respect to the objection to the drawings for not showing features of claim 5, that claim 5 is supported by Fig. 2 “Deliver Result 240”. However, this argument is not persuasive because reciting “deliver result” claim language in the drawings is not the same as illustrating the features being claimed as required under 37 CFR 1.83(a). The drawings must illustrate the feature claim 5 recites “delivering the result of the first operation to an entry of the issue queue occupied by a depending operation”.
On page 7 of the Remarks, Applicant argues, with respect the objection to the drawings for not showing features of claim 6, that claim 6 is supported by Fig. 2 “Accomplish with Bypass 242”. However, this argument is not persuasive because reciting “accomplish with bypass” claim language in the drawings is not the same as illustrating the features being claimed as required under 37 CFR 1.83(a). The drawings must illustrate the feature claim 6 recites “where the delivering is accomplished by a bypass path in the common write-back pipeline”.
On page 8 of the Remarks, Applicant argues that the amendment “one or more of” transverses the indefinite rejection of claim 13. However, this argument is not persuasive because the amendment “one or more of” does not clarify how the requesting, the arbitrating, the granting, or the completing, can include a second variable latency operation. It is still unclear in what sense these acts may “include” a second variable latency operation.
On pages 9-10 of the Remarks, Applicant argues:
Olson’s pick logic stall occurs in the context of the divide engine arbitration path, as the arbitration unit is waiting to select one of the competing divide engines, which is a stall affecting the variable latency instruction flow through the arbitration path. This is not the same as the instant application which halts the pick stage for a second operation, which is a fixed latency operation, which issues alongside the variable latency operation. The stall in Olson is a consequence of resource contention among divide engines. In the instant application, the mechanism deliberately delays picking a fixed latency instruction from the issue queue to create a downstream bubble in the common write-back pipeline for the variable latency result. These mechanisms are different.
However, this argument is not persuasive because a bubble inserted by the scheduler does not only affect the variable latency instruction flow as the instruction queue, scheduler, and issue unit are used by instructions other than the divide/variable latency instructions, see [0131]-[0132], and when the pick logic (in the scheduler) inserts a bubble it delays picking another instruction from the instruction queue. Specifically, [0062] discloses that each cycle the scheduler picks one instruction per slot to issue (which may be just one instruction in the embodiment that omits slots, see [0060]) and [0132] discloses that pick logic (in the scheduler) inserts bubbles to stall the pipeline. The cycle in which the scheduler inserts a bubble would delay picking an instruction (which may not be a divide instruction, see [0131]-[0132]) to issue at least in that cycle in the sense that an instruction that may have otherwise been picked for issue in that cycle would have to wait for the bubble to at least clear the issue stage in order to picked.
On page 10 of the Remarks, Applicant argues that Brooks, Colwell, and Kahle do not show or suggest the arbitrating step recited in claim 1. However, these arguments are not persuasive because the rejection does not rely on these references for teaching the arbitrating step.
On page 11 of the Remarks, Applicant argues:
However, upon closer review, Olson’s architecture does not include a common write-back pipeline, as in the instant application. In Olson, variable latency divide operations execute in divide engines and their results flow a dedicated post-engine path. The fixed latency integer operations flow through separate execution pipelines with their own write-back paths. Olson’s instruction pipeline is the general instruction commitment pipeline, not a pipeline that is architecturally shared with fixed latency execution states, as in the instant application.
However, this argument is not persuasive because it does not consider that the BRI of a “common write-back pipeline” may include separate execution units that are part of a common pipeline having a result commitment/write-back stage. Olson [0079] discloses that “any of the units illustrated in FIG. 2 may be implemented as one or more pipeline stages, to form an instruction execution pipeline that begins when thread fetching occurs in IFU 200 and ends with result commitment by TLU 275.” This instruction execution pipeline would have stages in which the execution units 235-255 execute and commit/writes back their results (with stages common to at least the TLU 275), which the office action maps to as a common write-back pipeline. Claim 3 only requires that the inserting of the result occurs at an execution stage of the common write-back pipeline, which is taught by Olson [0125] disclosing that the final quotient/result is inserted back into the pipeline via a requested bubble inserted by the scheduler and [0128] disclosing that the bubble is requested by the divide engine, which indicates that the bubble is used to insert the result at an execution stage corresponding to the divide engine in the common write-back pipeline.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 5 “delivering the result of the first operation to an entry of the issue queue occupied by a depending operation”. While Fig. 7 shows delivering the variable latency operation result to a dependent operation pipeline, the dependent operation pipeline is shown to be separate from the issue queue. The figures do not show an entry of the issue queue occupied by a depending operation that the result is delivered to.
Claim 6 “where the delivering is accomplished by a bypass path in the common write-back pipeline”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites “the requesting [includes] a second variable latency operation”. It is unclear how the requesting to complete the first operation described in claim 1 includes a second variable latency operation- does the requesting to complete the first operation include performing a second variable latency operation or does this limitation mean requesting to complete a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim 13 recites “the arbitrating [includes] a second variable latency operation”. It is unclear how the arbitrating for an opening described in claim 1 includes a second variable latency operation- does the arbitrating for the opening include performing a second variable latency operation or does this limitation mean arbitrating for an opening for a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim 13 recites “the granting [includes] a second variable latency operation”. It is unclear how the granting to complete the first operation described in claim 1 includes a second variable latency operation- does the granting to complete the first operation include completing a second variable latency operation or does this limitation mean granting to complete a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim 13 recites “the completing [includes] a second variable latency operation”. It is unclear how the completing the first operation described in claim 1 includes a second variable latency operation- does completing the first operation include completing a second variable latency operation or does this limitation mean completing a second variable latency operation? For purposes of examination, the latter interpretation will be taken.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 9-11, and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Olson US 2013/0179664 in view of Brooks US 7,373,489.
Regarding claim 1, Olson teaches:
1. A processor-implemented method for instruction execution comprising:
accessing a processor core (Fig. 2 core 100), wherein the processor core supports variable latency operations ([0079]: the FGU executes operations in a variable number of cycles (i.e., supports variable latency operations)), wherein the processor core includes an execution pipeline (Fig. 2, 240-255 are an execution pipeline), wherein the execution pipeline is coupled to an issue queue (Fig. 2 and 7: scheduler unit 225, issue unit 230, and arbitration unit 710 are an issue queue, see also Fig. 8 showing an instruction queue in the scheduler unit), and wherein the issue queue is coupled to a common write-back pipeline ([0079] describes that the units of Fig. 2 may be implemented as pipeline stages to form a pipeline that ends with result commitment, the stages of the pipeline corresponding to the execution units 235-255 to the result commitment are a common write-back pipeline);
issuing, by the issue queue, a first operation to a first execution engine within the execution pipeline, wherein the first operation is a variable latency operation ([0050]: the issue unit issues instructions to FGU 255 (which may include a variable latency operation, see [0079]), and the FGU includes a divide engine 310, see [0082], which is a first execution engine that may execute the operation);
issuing, by the issue queue, one or more additional operations to one or more additional execution engines in the execution pipeline, wherein at least one of the one or more additional operations is a fixed latency operation ([0050]: the issue unit issues instructions to EXU1, i.e., one or more additional execution engines);
executing the first operation ([0050]: the instructions issued to FGU 255 are executed by FGU 255);
requesting, by a control logic, to the issue queue, to complete the first operation, when the first operation finishes execution within the first execution engine ([0128] and [0136]: control unit 910 in the divide engine 310 requests to the arbitration unit 710 to pass its results along (i.e., to complete the first operation) when it has produced the result (i.e., when the operation finishes execution within the engine));
arbitrating, by the issue queue, for an opening, wherein the opening is in the common write-back pipeline ([0128]: the arbitration unit arbitrates among multiple received requests from the divide engines by selecting a request to grant (which may include waiting for the post-engine to become available before selecting a request to grant) and requesting a bubble in the pipeline for the request, selecting (or waiting and then selecting) a request arbitrates among the multiple requests for the bubble/opening that the arbitration unit requests, and the opening is used to commit results by inserting the final quotient back into the instruction pipeline, see [0125] and [0132], which indicates that the opening is in the common write-back pipeline), wherein the arbitrating comprises halting, by the issue queue, a pick stage for a second operation within the one or more additional operations ( [0132] describes the pick logic/stage inserting the bubbles/pipeline stalls, which stalls the pick stage for instructions in the instruction queue (as the pick stage would otherwise pick the instructions from the instruction queue, see also Fig. 8), which includes a second operation within the one or more additional operations as the instruction queue stores instructions other than divide instructions, see [0131]);
granting, by the issue queue, to complete the first operation, wherein the granting is based on the arbitrating (by granting the request to the engine, see [0128], and inserting a bubble for the final quotient (based on arbitrating for the bubble), see [0063] and [0125], the issue queue grants to complete the first operation based on the arbitrating); and
completing the first operation, wherein the completing includes inserting, at the opening in the common write-back pipeline, a result of the first operation ([0125] and [0132]: the final quotient (i.e., a result of the first operation) is inserted at the bubble/opening to commit the results, which completes the operation).
Olson does not explicitly teach fixed latency operations or the additional operations being fixed latency operations.
However, Brooks teaches fixed latency operations (col 1 lines 16-17 discloses integer instructions that are configured to execute in an integer pipeline of a particular depth, which are fixed latency operations)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the integer instructions of Olson (see [0065]) to execute in a pipeline/execution unit of a particular depth as taught by Brooks such that the integer instructions of the combination would be fixed latency operations. One of ordinary skill in the art would have been motivated to make this modification to improve scheduling of the instructions since fixed latency instructions with known execution times can be scheduled more efficiently than variable latency instructions.
Claim 19 is directed to a non-transitory computer readable medium storing code that generates logic for performing the method of claim 1 and is rejected for the same reasons as claim 1.
Claim 20 is directed to a computer system comprising one or more processors executing instructions stored on memory to perform the method of claim 1 and is rejected for the same reasons as claim 1, see also Olson [0024] disclosing memory storing executable instructions.
Regarding claim 3, Olson in view of Brooks teaches:
3. The method of claim 2 wherein the inserting occurs at an execution stage of the common write-back pipeline (Olson [0128]: the request for a bubble is based on the request from the engine 310, i.e., an execution stage of the pipeline corresponding to engine 310 needs the bubble to insert the final quotient/result (see also [0125] describing inserting the final quotient back into the pipeline via the requested bubble)).
Regarding claim 9, Olson in view of Brooks teaches:
9. The method of claim 1 wherein the arbitrating comprises stalling, by the issue queue, the first operation (Olson [0128]: if the post-engine is not available, the arbitration unit arbitrates among multiple requests from the divide engines by stalling the divide engines until the post-engine is available, which stalls the first operation at the engine, and then selecting one of the requests once it becomes available).
Regarding claim 10, Olson in view of Brooks teaches:
10. The method of claim 1 further comprising completing the one or more additional operations (Olson [0078]-[0079]: TLU 275 completes instructions, including the instructions executed by EXU1 (i.e., the one or more additional operations) at the end of the instruction pipeline).
Regarding claim 11, Olson in view of Brooks teaches:
11. The method of claim 1 wherein the processor core includes one or more additional execution pipelines (Olson Fig. 1, EXU0 235 is an additional execution pipeline).
Regarding claim 13, Olson in view of Brooks teaches:
13. The method of claim 1 wherein one or more of the requesting, the arbitrating, the granting, and the completing include a second variable latency operation (Olson since FGU 255 processes variable latency operations, see [0079], and the issue unit issues instructions to FGU 255, see [0050], the issue unit may issue a second variable latency instruction for which arbitrating, granting, and completing may be performed for).
Regarding claim 14, Olson in view of Brooks teaches:
14. The method of claim 1 wherein the variable latency operation is identified by the issue queue (Olson [0050]: the issue unit identifies instructions, including variable latency operations executed by the FGU, in order to issue them to the appropriate execution unit, see also [0062] disclosing that the instruction queue in the scheduler stores decoded instructions, which would also identify a variable latency operation by decoding it).
Regarding claim 15, Olson in view of Brooks teaches:
15. The method of claim 1
While Olson teaches executing a floating-point square root operation in a divide unit, see [0027], which is in the FGU 255 which executes certain types of operations in a variable number of cycles, see [0079] and [0082], Olson does not explicitly teach the floating-point square root operation being a variable latency operation.
However, Brooks further teaches square-root instruction that is a variable latency operation (col 12 lines 35-37: square-root instructions may execute in a variable number of cycles).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the floating-point square root operation of Olson to be a variable latency operation as taught by Brooks. One of ordinary skill in the art would have been motivated to make this modification to reduce timing constraints and allow more flexibility in how the floating-point square root operation is executed.
Regarding claim 16, Olson in view of Brooks teaches:
16. The method of claim 1
While Olson teaches executing a floating-point divide operation in a divide unit, see [0027], which is in the FGU 255 which executes certain types of operations in a variable number of cycles, see [0079] and [0082], Olson does not teach explicitly teach the floating-point divide operation being a variable latency operation.
However, Brooks further teaches a divide operation that is a variable latency operation (col 12 lines 35-37: divide instructions may execute in a variable number of cycles).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the floating-point divide operation of Olson to be a variable latency operation as taught by Brooks. One of ordinary skill in the art would have been motivated to make this modification to reduce timing constraints and allow more flexibility in how the floating-point divide operation is executed.
Regarding claim 17, Olson in view of Brooks teaches:
17. The method of claim 1 wherein the execution of the variable latency operation is not pipelined (Olson [0070]: instructions implemented by the FGU may block issue until complete, i.e., the execution of the instructions is not pipelined).
Regarding claim 18, Olson in view of Brooks teaches:
18. The method of claim 1 wherein the processor core executes one or more instructions out of order (Olson [0027]: each core executes instructions out of order).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Olson US 2013/0179664 in view of Brooks US 7,373,489 and Colwell US 6,101,597.
Regarding claim 5, Olson in view of Brooks teaches:
5. The method of claim 3 further comprising delivering the result of the first operation to the issue queue for a depending operation, wherein the depending operation includes a dependency on the result of the first operation ([0064]: the issue unit may read source operands of dependent instructions directly from the result bus).
Olson in view of Brooks does not teach delivering the result to an entry of the issue queue occupied by a depending operation
However, Colwell teaches that a result may provide/deliver an input operand to waiting instructions buffered in the reservation station to indicate that the source operand is ready for dispatch along with instructions using the operand, see col 3 lines 56-61.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Olson to deliver the source operand of a dependent instruction (i.e., the result of the first operation) to an entry occupied by the dependent instruction as taught by Colwell. One of ordinary skill in the art would have been motivated to make this modification to enable faster dispatch of dependent instructions with their source operands once the source operands are ready.
Regarding claim 6, Olson in view of Brooks and Colwell teaches:
6. The method of claim 5 wherein the delivering is accomplished by a bypass path in the common write-back pipeline (Olson [0064] discloses that the source operand may be bypassed directly from the execution unit result bus, the path used for the bypassing is a bypass path in the common write-back pipeline).
Regarding claim 7, Olson in view of Brooks and Colwell teaches:
7. The method of claim 5 further comprising writing the result of the first operation, in a writeback stage of the common write-back pipeline, to a register file (Olsen [0064] discloses that the results may be sourced from register files indicating the architectural state and [0078]-[0079] discloses committing working results to the architectural state, which indicates that the results are written to a register file and the corresponding stage is a writeback stage of the common write-back pipeline).
Regarding claim 8, Olson in view of Brooks and Colwell teaches:
8. The method of claim 7 further comprising reading, from the register file, the results of the first operation (Olson [0064]: the results are sourced from/read from the register file).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Olson US 2013/0179664 in view of Brooks US 7,373,489 and Kahle US 6,728,866.
Regarding claim 12, Olson in view of Brooks teaches:
12. The method of claim 11
Olson in view of Brooks does not teach:
wherein each execution pipeline in the one or more additional execution pipelines includes a unique issue queue.
However, Kahle teaches a unique issue queue for each functional unit, see col 7 lines 54-59 and Fig. 3. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Olson to include a unique issue queue for the execution units as taught by Kahle such that EXU0 of the combination would include a unique issue queue. One of ordinary skill in the art would have been motivated to make this modification to issue instructions without the delay associated with determining which execution unit to choose (Kahle col 7 lines 62-65).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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