Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are currently pending in the present application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The IDSs dated 31 October 2024, 03 July 2025, and 27 March 2026 were considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re: claim 4, the meaning of the limitation “a portion of the inner surface of the bottomed hole” is unclear. It is not clear as to whether the limitation refers to the portion of the inner surface of the bottomed hole as recited in claim 3 or if some other component is being referenced. For the purpose of examining the present claim, the limitation has been construed as referring to the portion of the inner surface of the bottomed hole as recited in claim 3.
Re: claim 5, because it depends upon claim 4, it is likewise rejected.
Re: claim 6, the meaning of the limitation “an inner side of the outer edge of the bottomed hole” is unclear. It is not clear whether this limitation refers to the inner side of the outer edge of the bottomed hole recited in claim 1 or whether some other component is being referenced. For the purpose of examining the present claim, the limitation has been construed as referencing the inner side of the outer edge of the bottomed hole recited in claim 1.
Re: claim 18, the meaning of the limitation “the first bottomed hole” is unclear. It is not clear as to whether the limitation refers to the bottomed hole recited in claim 1 or whether some other hole is being referenced. For the purpose of examining the present claim, the limitation has been construed as referencing the bottomed hole recited in claim 1.
Re: claim 19, because it depends upon claim 18, it is likewise rejected.
Allowable Subject Matter
Claims 1-3, 7-17, and 20 are allowed.
Claims 4-6 and 18-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re: independent claim 1, prior art reference Park (US 20150346529), now made of record, discloses an active matrix substrate 100 (Fig. 2) including a display region 300 (Fig. 1) including a plurality of pixel areas PX arrayed in a matrix shape in a row direction and a column direction (Figs. 1, 2 disclose matrix array), and a non-display region positioned in a periphery of the display region (Fig. 1, the region disposed outwardly from display region 300), in which a peripheral circuit 400, 500 is disposed in the non-display region (disposition disclosed in Fig. 1); the active matrix substrate comprising: a substrate 110 (Fig. 4); a pixel TFT Tr (Fig. 3) supported by the substrate and provided corresponding to each of the plurality of pixel areas (support & provision disclosed in Figs. 1-3); an organic insulating layer 140 (para. 57 discloses organic) disposed above the pixel TFT (disposition above TFT disclosed in Fig. 4) and positioned in the display region (Figs. 1, 3, 4) and an inorganic insulating layer 150 (paras. 83-85 disclose inorganic) disposed on the organic insulating layer (disposition disclosed in Fig. 4), wherein the organic insulating layer and the inorganic insulating layer are provided with a dual-layer hole structure portion (Fig. 4), the dual-layer hole structure portion includes a through-hole H2 provided in the inorganic insulating layer 150 (provision disclosed in Fig. 4), a hole provided in the organic insulating layer 140 and positioned below the through-hole (provision & positioning disclosed in Fig. 4). However, Park does not explicitly disclose that the pixel TFT comprises an oxide semiconductor; that the organic insulating layer is positioned above at least a portion of the non-display region when viewed from a normal direction of the substrate; that the inorganic insulating layer is disposed in contact with an upper surface of the organic insulating layer; that the hole in the organic insulating layer is bottomed; and that an entirety of the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from the normal direction of the substrate, and the dual-layer hole structure portion is disposed between the display region and the peripheral circuit.
Also, re: independent claim 1, prior art reference Kim (US20150378208), now made of record, discloses an active matrix substrate (Figs. 4, 5) including a display region (Fig. 1) including a plurality of pixel areas (Fig. 2) arrayed in a matrix shape in a row direction and a column direction (matrix array disclosed in Fig. 1), and a non-display region positioned in a periphery of the display region (Fig. 1, the perimeter of substrate 110); the active matrix substrate comprising: a substrate 110; a pixel TFT Qh, Ql (Fig. 2) supported by the substrate (Figs. 3, 4) and provided corresponding to each of the plurality of pixel areas (provision disclosed in Fig. 2, 3), the pixel TFT including an oxide semiconductor layer 154h, 154l (para. 55 discloses oxide); an organic insulating layer 360, 365 (para. 78 discloses organic) disposed above at least the oxide semiconductor layer of the pixel TFT and positioned in the display region (disposition & positioning disclosed in Figs. 4 & 5 where the oxide semiconductor layer is disposed in a sublayer above the sublayer comprising the pixel TFT); and an inorganic insulating layer 370 (para. 84 discloses inorganic) disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer (contact disclosed in Fig. 5), wherein the organic insulating layer and the inorganic insulating layer are provided with a dual-layer hole structure portion (Fig. 5, portion that includes 1362), the dual-layer hole structure portion includes a through-hole (Fig. 5, the through-hole in 370 that corresponds to groove 1362) provided in the inorganic insulating layer 370, a bottomed hole 1362 provided in the organic insulating layer 360 and positioned below the through-hole (positioning disclosed in Fig. 5), and an entirety of the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from the normal direction of the substrate (positioning disclosed in Fig. 5). However, Kim does not explicitly disclose a peripheral circuit disposed in the non-display region; that the organic insulating layer is positioned in at least a portion of the non-display region when viewed from a normal direction of the substrate; and that the dual-layer hole structure portion is disposed between the display region and the peripheral circuit.
Conclusion
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/ANGELA M. MEDICH/Primary Examiner, Art Unit 2871
