Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (Pub NO. US 2004/0207387 A1; hereinafter Chung) in view of Kim et al. (Pub NO. US 2007/0296448 A1; hereinafter Kim).
Regarding Claim 1, Chung teaches a socket ranking method for a semiconductor test apparatus, the semiconductor test apparatus comprising a plurality of sockets and a storage device and configured to load semiconductor chips into sockets, respectively, and perform tests thereon (a socket ranking method in Fig. 4-Fig. 6; See [0027]-[0053]), the socket ranking method comprising:
loading the semiconductor chips into the sockets, and performing a primary determination for the loaded semiconductor chips as one of Pass or Fail based on first criteria (See step S100 and S110 in Fig. 4 and first criteria is OPEN test in Fig. 6; Se [0027]-[0053]);
performing a secondary determination for the semiconductor chips reloaded into the sockets, as one of Pass or Fail based on second criteria (secondary determination is SHORT test based on second criteria in Fig. 6; See [0027]-[0053]);
calculating a point of each of the sockets and storing the point in the storage device, by adding or deducting the point for each of the sockets, based on the result of the primary determination and a result of the secondary determination (calculating a point of each of the sockets 32, 33, 34 based on test results in Fig. 6; See [0027]-[0053]); and
assigning priority to each of the sockets based on the point calculated therefor and storing the assigned priority in the storage device (priority is assigned for each socket based on test results PASS/FAIL in fig. 6; See [0027]-[0053]).
Chung is silent about reloading the semiconductor chips determined as Fail based on a result of the primary determination into the sockets;
Kim teaches regarding semiconductor testing (See abstract) reloading the semiconductor chips determined as Fail based on a result of the primary determination into the sockets (reloading semiconductor chip in sorting buffer in step 243, 244 based on fail test result in step 241 in Fig. 7; See [0088]-[0110]);
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by reloading the semiconductor chips determined as Fail based on a result of the primary determination into the sockets, as taught by Kim in order to achieve efficient testing for semiconductor chip (Kim; [0003]).
Regarding Claim 2, Chung in view of Kim teaches the socket ranking method of claim 1. Chung is silent about the reloading comprises reloading the semiconductor chips into remaining sockets except for the sockets into which the semiconductor chips determined as Fail have been loaded at the primary determination
Kim further teaches wherein the reloading comprises reloading the semiconductor chips into remaining sockets except for the sockets into which the semiconductor chips determined as Fail have been loaded at the primary determination (sorting buffer and assorting unit at step 244 is different location from the steps above in Fig. 7; See [0088]-[0110]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by the reloading comprises reloading the semiconductor chips into remaining sockets except for the sockets into which the semiconductor chips determined as Fail have been loaded at the primary determination, as taught by Kim in order to achieve efficient testing for semiconductor chip (Kim; [0003]).
Regarding Claim 3, Chung in view of Kim teaches the socket ranking method of claim 1. Chung further teaches wherein the reloading comprises reloading the semiconductor chips into the sockets into which the semiconductor chips determined as Pass have been loaded at the primary determination (reloading for second test is same socker 32 for DUT in Fig. 6; See [0044]-[0048]).
Regarding Claim 4, Chung in view of Kim teaches the socket ranking method of claim 1. Chung further teaches wherein the first criteria are identical to the second criteria (all criteria are same to compare with reference data 360 in fig. 6; See [0044]-[0048]).
Regarding Claim 5, Chung in view of Kim teaches the socket ranking method of claim 1, wherein the calculating comprises tracing the sockets, into which the semiconductor chips have been loaded at the primary determination, respectively, and the sockets, into which the semiconductor chips have been reloaded at the secondary determination, respectively (tracing sockets 32, 33 or 34 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]), and
calculating the point of each of the sockets by selecting a first group of the sockets, into which the semiconductor chips determined as Fail according to the secondary determination have been loaded at the primary determination (first group of socket is 32 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]), and
a second group of the sockets, into which the semiconductor chips have been reloaded at the secondary determination, and adding the point of each of the sockets to a corresponding one from among the first group of the sockets and the second group of the sockets (second group of socket is 33 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]).
Regarding Claim 6, Chung in view of Kim teaches the socket ranking method of claim 1, wherein the calculating comprises, tracing the sockets, into which the semiconductor chips have been loaded, respectively, at the primary determination, and calculating the point of each of the sockets by selecting a first group of the sockets (first group of socket is 32 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]), into which the semiconductor chips determined as Pass at the secondary determination have been loaded at the primary determination, and deducting the point of each of the socket for a corresponding one from among the first group of the sockets (into which semiconductor chips PASS/FAIL have been loaded for primary determination OPEN and secondary determination SHORT and socket ranking is reduced/added by PASS/FAIL in Fig. 6; See [0044]-[0048]).
Regarding Claim 7, Chung in view of Kim teaches the socket ranking method of claim 1. Chung further teaches wherein the calculating comprises calculating the point of each of the sockets by selecting a first group of the sockets, in which the semiconductor chips are determined as Pass have been loaded at the secondary determination, and adding the point of each of the sockets to a corresponding one from among the first group of the sockets (into which semiconductor chips PASS/FAIL have been loaded for primary determination OPEN and secondary determination SHORT and socket ranking is reduced/added by PASS/FAIL in Fig. 6; See [0044]-[0048]).
Regarding Claim 8, Chung teaches a socket ranking method for a semiconductor test apparatus, the semiconductor test apparatus comprising a plurality of sockets and a storage device, and configured to load semiconductor chips into sockets (a socket ranking method in Fig. 4-Fig. 6; See [0027]-[0053]), respectively, and perform tests thereon, the socket ranking method comprising:
loading the semiconductor chips into the sockets, and performing a primary assignment of one or more types of first indicators to the loaded semiconductor chips (See step $100 and $110 in Fig. 4 and first criteria is OPEN test in Fig. 6; Se [0027]-[0053]);
performing a secondary assignment of one or more types of second indicators to the reloaded semiconductor chips based on a criterion (secondary determination is SHORT test based on second criteria in Fig. 6; See [0027]-[0053]);
adding or deducting a point to each of the sockets based on the first indicators assigned to the semiconductor chips at the primary assignment and the second indicators assigned to the semiconductor chips at the secondary assignment (adding or deducing point of each of the sockets 32, 33, 34 based on each test result has different indicators in Fig. 6; See [0027]-[0053]),
calculating the point for each of the sockets, and storing the calculated point in the storage device (See [0027]-[0053]); and
assigning priority to each of the sockets based on the point calculated therefor and storing the assigned priority in the storage device (priority is assigned for each socket based on test results PASS/FAIL in fig. 6; See [0027]-[0053]).
Chung is silent about reloading the semiconductor chips into some of the sockets based on the first indicators assigned to semiconductor chips;
Kim teaches regarding semiconductor testing (See abstract) reloading the semiconductor chips into some of the sockets based on the first indicators assigned to semiconductor chips (reloading semiconductor chip in sorting buffer in step 243, 244 based on fail test result in step 241 in Fig. 7; See [0088]-[0110]);
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by reloading the semiconductor chips into some of the sockets based on the first indicators assigned to semiconductor chips, as taught by Kim in order to achieve efficient testing for semiconductor chip (Kim; [0003]).
Regarding Claim 9, Chung in view of Kim teaches the socket ranking method of claim 8. Chung further teaches wherein the calculating comprises tracing the sockets, into which the indicators of each of the semiconductor chips have been loaded at the primary assignment and the sockets (tracing sockets 32, 33, 34 for semiconductor 330 has been loaded for primary assignment OPEN in Fig. 6; See [0042]-[0053]), into which the indicators of each of the semiconductor chips have been reloaded at the secondary assignment (semiconductor 330 has been loaded for secondary assignment SHORT in Fig. 6; See [0042]-[0053]), and calculating the point for each of the sockets based on the one or more types of the first indicators and the one or more types of the second indicators (socket point is calculated based on first indicator of OPEN test and second indicator of SHORT test in Fig. 6; See [0042]-[0053]).
Regarding Claim 10, Chung in view of Kim teaches the socket ranking method of claim 9. Chung further teaches wherein the calculating comprises calculating the point for each of the socket, for the semiconductor chips, for which the first indicators assigned at the primary assignment and the second indicators assigned at the secondary assignment are all identical (calculating points for each sockets 32, 33 or 34 into which semiconductor chips have been loaded for primary indicator OPEN and secondary indicator SHORT in Fig. 6; See [0044]-[0048]), by selecting a first group of the sockets, into which corresponding ones of the semiconductor chips assigned with the first indicators at the primary assignment have been loaded, respectively (first group of socket is 32 into which semiconductor chips have been loaded for primary determination OPEN in Fig. 6; See [0044]-[0048]), and a second group of the sockets into which the corresponding ones of the semiconductor chips assigned with the second indicators at the secondary assignment have been loaded, and adding the point for each of the sockets to a corresponding one from among the first group of the sockets and the second group of the sockets (second group of socket is 33 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]).
Regarding Claim 11, Chung in view of Kim teaches the socket ranking method of claim 9. Chung further teaches wherein the calculating comprises calculating the point for each of the sockets based on the first indicators assigned to the semiconductor chips at the primary assignment and the second indicators assigned to the semiconductor chips at the secondary assignment, for the semiconductor chips (tracing sockets 32, 33 or 34 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]), for which at least some of the indicators assigned at the primary assignment and the indicators assigned at the secondary assignment are not identical (all indicators of OPEN, SHORT are not identical in fig. 6; See [0088]-[0110]),
calculating the point for each of the sockets by selecting a first group of the sockets, into which the corresponding semiconductor chips assigned with the first indicators at the primary assignment are loaded (first group of socket is 32 into which semiconductor chips have been loaded for primary determination OPEN in Fig. 6; See [0044]-[0048]), and a second group of the sockets, into which the corresponding semiconductor chips assigned with the second indicators at the secondary assignment are loaded, and deducting the point of each of the sockets for a corresponding one from among the first group of the socket and the second group of the sockets (second group of socket is 33 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]).
Regarding Claim 12, Chung in view of Kim teaches the socket ranking method of claim 11. Chung further teaches wherein the calculating comprises calculating the point for each of the sockets, for the semiconductor chips tracing sockets 32, 33 or 34 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]), for which at least some of the first indicators assigned at the primary assignment and the second indicators assigned at the secondary assignment are not identical (all indicators of OPEN, SHORT are not identical in fig. 6; See [0088]-[0110]), by selecting a first group of the sockets, into which the semiconductor chips having the first indicators have been loaded at the primary assignment (first group of socket is 32 into which semiconductor chips have been loaded for primary determination OPEN in Fig. 6; See [0044]-[0048]), and
a second group of the sockets, into which the semiconductor chips having the second indicators, relatively more type of which are different from the first indicators, have been loaded at the secondary assignment, and deducting relatively more points for the first group of the sockets and the second group of the sockets (second group of socket is 33 into which semiconductor chips have been loaded for primary determination OPEN and secondary determination SHORT in Fig. 6; See [0044]-[0048]).
Claim(s) 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of HAN et al. (Pub NO. US 2023/0213573 A1; hereinafter Han).
Regarding Claim 13, Chung teaches a semiconductor test method for a semiconductor test apparatus, the semiconductor test apparatus comprising a plurality of sockets and a storage device, and configured to load semiconductor chips into sockets (a socket ranking method in Fig. 4-Fig. 6; See [0027]-[0053]), respectively, and perform tests thereon, the semiconductor test method comprising:
loading the semiconductor chips into the sockets, performing repeatedly tests on the loaded semiconductor chips (See step $100 and $110 in Fig. 4 for repeated test in Fig. 6; Se [0027]-[0053]),
calculating a point for each of the sockets according to first criteria (point is calculated according to first criteria/compare with reference data 360 in fig. 6; See [0027]-[0053]), and
storing the point in the storage device (See [0046]);
selecting a group of sockets to be used for tests to each of the sockets stored in the storage device (selecting sockets 32, 33, 34 based on priority in fig. 6); and
loading the semiconductor chips into the selected group of the sockets to each of the sockets, and performing the tests (See step $100 and $110 in Fig. 4 for repeated test in Fig. 6; Se [0027]-[0053]).
Chung is silent about assigning priority to each of the sockets based on the point for each of the sockets stored in the storage device, and storing the assigned priority to each of the sockets in the storage device; and selecting and loading the semiconductor chips based on the priority.
Han teaches regarding semiconductor testing assigning priority to each of the sockets based on the point for each of the sockets stored in the storage device (See [0018]-[0019], [0021], [0083]-[0084], [0116]), and storing the assigned priority to each of the sockets in the storage device; and selecting and loading the semiconductor chips based on the priority (See [0018]-[0019], [0021], [0083]-[0084], [0116]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by assigning priority to each of the sockets based on the point for each of the sockets stored in the storage device, and storing the assigned priority to each of the sockets in the storage device; and selecting and loading the semiconductor chips based on the priority, as taught by Han in order to achieve efficient testing for semiconductor chip (Han; abstract).
Regarding Claim 14, Ching in view of Han teaches the semiconductor test method of claim 13. Chung further teaches wherein, the calculating the point for each of the sockets comprises accumulating the point for each of the sockets calculated by repeatedly performing the tests on the loaded semiconductor chips (point is accumulated by performing test in Fig. 6; See [0042]-[0053]), the storing point in the storage device comprises storing the accumulated point in the storage device (See [0046]),
Chung is silent about the assigning the priority to each of the sockets comprises assigning the priority to each of the sockets based on the point stored in the storage device by accumulating the point for each of the sockets, and the storing the assigned priority to each of the sockets in the storage device comprises storing the assigned priority to each of the sockets in the storage device.
Han teaches regarding semiconductor testing the assigning the priority to each of the sockets comprises assigning the priority to each of the sockets based on the point stored in the storage device by accumulating the point for each of the sockets (See [0018]-[0019], [0021], [0083]-[0084], [0116]), and the storing the assigned priority to each of the sockets in the storage device comprises storing the assigned priority to each of the sockets in the storage device (See [0018]-[0019], [0021], [0083]-[0084], [0116]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by assigning the priority to each of the sockets comprises assigning the priority to each of the sockets based on the point stored in the storage device by accumulating the point for each of the sockets, and the storing the assigned priority to each of the sockets in the storage device comprises storing the assigned priority to each of the sockets in the storage device, as taught by Han in order to achieve efficient testing for semiconductor chip (Han; abstract).
Regarding Claim 15, Ching in view of Han teaches the semiconductor test method of claim 14. Chung further teaches wherein, the calculating the point for each of the sockets comprises, as the tests on the semiconductor chips are repeated (See the repeated tests for OPEN/SHORT/LEAKAGE in fig. 6; See [0042]-[0053]), assigning weights to the point for each of the sockets (assigning weights of each sockets 32, 33, 34 based on test results in Fig. 6; See [0042]-[0053]), for each of which the point has been calculated relatively recently based on a reference point in time (See the reference 360 in Fig. 6; See [0042]-[0053]), and accumulating the assigned weights (See [0042]-[0053]).
Regarding Claim 16, Ching in view of Han teaches the semiconductor test method of claim 13. Chung further teaches further comprising: deleting the point for each of the sockets (point depends on PASS/FAIL in Fig. 6; See [0042]-[0053]).
Chung is silent about the priority for each of the sockets stored in the storage device based on second criteria or an input to the semiconductor test apparatus.
Han teaches regarding semiconductor testing the priority for each of the sockets stored in the storage device based on second criteria or an input to the semiconductor test apparatus (See [0018]-[0019], [0021], [0083]-[0084], [0116]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by using the priority for each of the sockets stored in the storage device based on second criteria or an input to the semiconductor test apparatus, as taught by Han in order to achieve efficient testing for semiconductor chip (Han; abstract).
Regarding Claim 17, Ching in view of Han teaches the semiconductor test method of claim 14. Chung further teaches wherein the calculating the point for each of the sockets comprises calculating the point for each of the sockets by normalizing and accumulating the point for each of the sockets that have been calculated by repeatedly performing the tests on the semiconductor chips (normalizing and accumulating each test result for each socket 31, 33, 34 in Fig. 6; See [0042]-[0053]).
Chung is silent about the assigning the priority comprises assigning the priority to each of the sockets based on the accumulated point for each of the sockets.
Han teaches regarding semiconductor testing assigning the priority comprises assigning the priority to each of the sockets based on the accumulated point for each of the sockets (See [0018]-[0019], [0021], [0083]-[0084], [0116]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the system of Chung by assigning the priority comprises assigning the priority to each of the sockets based on the accumulated point for each of the sockets, as taught by Han in order to achieve efficient testing for semiconductor chip (Han; abstract).
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 18, none of the prior art fairly teaches or suggests the semiconductor test method of claim 13, wherein, in a case where a number of semiconductor chips to be tested at a present time point is n, a first group of the sockets to be used for the tests are selected based on the priority of each of the sockets such that the sockets each having nth or greater priority are selected as the first group of the sockets , loading the semiconductor chips into the first group of the sockets, respectively, turning off the sockets each having less than nth priority, loading the n semiconductor chips into the first group of the sockets, and performing the tests on the semiconductor chips loaded into the first group of the sockets.
Regarding Claim 19, none of the prior art fairly teaches or suggests the semiconductor test method of claim 13, wherein in a case where a number of semiconductor chips to be tested at a present time point is n, the selecting comprises selecting a first group of the sockets to be used for the tests based on the priority of each of the sockets such that a first group of the sockets each having mth or greater priority are selected as the first group of the sockets, and in a case where n is greater than m (n>m), loading the semiconductor chips into the first group of the sockets, respectively, and performing the tests on the loaded semiconductor chips such that the sockets each having less than mth priority are turned off, the m semiconductor chips are first loaded into the sockets each having mth or greater priority, and tested, and remaining (n-m) semiconductor chips are loaded and tested after completing the tests on the m semiconductor chips.
Regarding Claim 20, none of the prior art fairly teaches or suggests the semiconductor test method of claim 13, wherein in a case where a number of semiconductor chips to be tested at a present time point is n, selecting a first group of the sockets to be used for the tests based on the priorities of the sockets such that the sockets each having mth or greater priority are selected as the first group of the sockets, and in a case where n is less than or equal to m (n≤m), loading the semiconductor chips are loaded into the first group of the sockets, respectively, turning off the sockets each having less than nth priority, loading n semiconductor chips into the sockets each having nth or greater priority, and performing the tests on the n semiconductor chips.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Co et al. (Pub NO. US 2011/0050268 A1) discloses Memory Module Testing.
b. Park et al. (Patent NO. US 7,479,793 B2) discloses Apparatus for Testing Semiconductor.
c. Hama et al. (Patent NO. US 5,818,219) discloses Semiconductor Test System.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
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/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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