CTNF 18/933,321 CTNF 89467 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-20 are pending. Claims 11-20 have been withdrawn as per Applicants' request. Information Disclosure Statement The information disclosure statement (IDS) submitted on October 31, 2024 is/are in compliance with the provisional of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions 08-25 AIA Applicant's election with traverse of Group 1, claims 1-10 in the reply filed on April 07, 2026 is acknowledged. The traversal is on the ground(s) that “a search for Groups I-III would necessarily overlap” . This is not found persuasive because the three groups of inventions have acquired a separate status in view of their different classifications and are directed to different fields of search . The requirement is still deemed proper and is therefore made FINAL. 08-05 AIA Claim s 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II and III , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on April 07, 2026 . Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 6, and 9 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Halaharivi et al. (US 2024/0160577) (hereinafter Hala) (published May 16, 2024) . Regarding Claim 1 , Hala discloses a data storage device, comprising: a memory device; and “The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such ” (Hala [0029]) a controller coupled to the memory device, wherein the controller is configured to: “ The memory sub-system controller 115 can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof” (Hala [0037]) receive an invalidation request, wherein the invalidation request includes one or more untranslated addresses; “ the invalidation requests may be received over a set of data channels for writes 736 into an AXI converter 726 that receives the invalidation requests from the host system 620 . The translation logic 602 can then place each incoming invalidation request into the set of invalidation queues 718 to be handled in an order received” (Hala [0107]) “In embodiments, the invalidation handler logic 750 detects an invalidation request within the set of invalidation queue 718, the invalidation request corresponding to a virtual address of the virtual addresses ” (Hala [0108] virtual addresses are untranslated ) issue an address translation request for the one or more untranslated addresses; “The controller in these systems can be configured to include an address translation circuit, more specifically referred to as an address translation service (ATS), that is to request the TA to perform certain address translations from a virtual (or logical) address to an available (or assigned) physical address of the memory device. In this way, the address translation circuit (or ATS) dynamically determines address translations based on the virtual address located in a corresponding memory command that is queued within host memory” (Hala [0020]) “ the address translation requests that missed at the ATC 716 are forwarded to an AXI converter 722, which sends out address translation requests to the host interface 208 over a set of address channels for reads 732 and destined to the TA 617 ” (Hala [0104]) “the invalidation request corresponding to a virtual address of the virtual addresses. The invalidation handler logic 750 can further cause address translations associated with the virtual address to be marked as invalid within the set of request staging queues 702, the set of pending response queues 704, the set of reordering buffers 714, and the cache (the ATC 716)” (Hala [0108]) receive a translated address for each untranslated address of the one or more untranslated addresses; and “ In response to the TA 617 providing the address translations, the address translations are received over a set of data channels 734 for reads and through an AXI converter 724” (Hala [0104]) determine whether the translated address matches a stored translated address. “the invalidation request corresponding to a virtual address of the virtual addresses. The invalidation handler logic 750 can further cause address translations associated with the virtual address to be marked as invalid within the set of request staging queues 702, the set of pending response queues 704, the set of reordering buffers 714, and the cache (the ATC 716) ” (Hala [0108] address that are associated are matches ) Regarding Claim 2 , Hala further discloses wherein the stored translated address is stored in an address translation cache (ATC). “As explained, the address translation circuit 413 can receive (or retrieve) an address translation request from a HIF circuit that is handling a memory command, request the TA perform a translation of a virtual address located within the memory command, and upon receiving the physical address, store a mapping between the virtual address and the physical address (also referred to as L2P mapping) in the ATC 416 ” (Hala [0081]) Regarding Claim 3 , Hala further discloses wherein the address translation request is issued to a translation agent (TA). “ the address translation requests that missed at the ATC 716 are forwarded to an AXI converter 722, which sends out address translation requests to the host interface 208 over a set of address channels for reads 732 and destined to the TA 617 ” (Hala [0104]) Regarding Claim 6 , Hala further discloses wherein the issuing, receiving, and determining occurs prior to issuing an invalidation completion for the invalidation request. “More specifically, when the invalidation handler logic 750 has confirmed the address translation circuit 713 and the HIF circuits 608 have purged queue, buffer, and cache entries of invalid address translations associated with an invalidation requests, the invalidation handler logic 750 may send an invalidation response to an AXI converter 728. The AXI converter 728 can place the invalidation response out on a set of data channels for writes 738 to the TA 617 at the host system 620 ” (Hala [0110] the invalidation completion response happens after all the translation and invalidation ) Regarding Claim 9 , Hala further discloses wherein prior to the issuing, the controller is configured to determine whether translated addresses have replaced at least one untranslated address in an address translation cache (ATC). “In some embodiments, the translation logic 602 further, for each incoming address translation request, determines whether the virtual address (or queue identifier) within the address translation request hits or misses at the cache (ATC 716) ” (Hala [0102] a hit would indicate that the translation is stored and replaced the untranslated address ) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim s 4, 5, 7, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hala (published May 16, 2024) as applied to claim s 1 and 6 above, and further in view of Ng et al. (US 2022/0206976) (hereinafter Ng) (published June 30, 2022) . Regarding Claim 4 , Hala disclosed the device of claim 1, but does not explicitly state wherein the controller is configured to perform a lookup operation and determine which command is to be completed before sending an invalidation completion. Ng discloses wherein the controller is configured to perform a lookup operation and determine which command is to be completed before sending an invalidation completion. “ a snapshot is taken of the contents of the DMA engine's ATB (step 302). The snapshot memorializes all ATB entries/responses that were stored prior to the invalidation request ” (Ng [0027]) “Then, the device flushes the snapshotted buffer contents by removing the address translation response at the head of the buffer (step 304), processing the response to perform one or more memory accesses and/or other associated action(s) (step 306) , and determining whether all snapshotted responses have been flushed from the ATB (step 308). Steps 304-308 may be repeated as necessary” (Ng [0028] the commands are looked up one at a time and flushed out to perform memory access ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the processing of request before the completion of the invalidation command in Ng with the system in Hala. The motivation for doing so would be to improve the consistency and efficiency of the address translation of memory by not needing to reload the translations or cause any conflicts for in flight operations. Regarding Claim 5 , Ng further discloses wherein the controller is configured to issue the invalidation completion upon completing the command. “ When all address translation responses that were buffered at the time of receipt of the invalidation request have been processed, and associated DMA operations involving the address translations have completed, the device responds to the invalidation request (step 310) ” (Ng [0029]) Regarding Claim 7 , Hala disclosed the device of claim 6, but does not explicitly state wherein the controller is configured to wait for data transfer completion for the untranslated address before issuing the invalidation completion. Ng discloses wherein the controller is configured to wait for data transfer completion for the untranslated address before issuing the invalidation completion. “ When all address translation responses that were buffered at the time of receipt of the invalidation request have been processed, and associated DMA operations involving the address translations have completed, the device responds to the invalidation request (step 310) ” (Ng [0029]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the processing of request before the completion of the invalidation command in Ng with the system in Hala. The motivation for doing so would be to improve the consistency and efficiency of the address translation of memory by not needing to reload the translations or cause any conflicts for in flight operations. Regarding Claim 8 , Hala disclosed the device of claim 6, but does not explicitly state wherein the controller is configured to wait for an entire command containing the untranslated address to complete before issuing the invalidation completion. Ng discloses wherein the controller is configured to wait for an entire command containing the untranslated address to complete before issuing the invalidation completion. “ When all address translation responses that were buffered at the time of receipt of the invalidation request have been processed, and associated DMA operations involving the address translations have completed, the device responds to the invalidation request (step 310) ” (Ng [0029]) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the processing of request before the completion of the invalidation command in Ng with the system in Hala. The motivation for doing so would be to improve the consistency and efficiency of the address translation of memory by not needing to reload the translations or cause any conflicts for in flight operations . 07-22-aia AIA Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hala (published May 16, 2024) as applied to claim 1 above, and further in view of JACOBI et al. (US 2011/0307662) (hereinafter Jacobi) (published December 15, 2011) . Regarding Claim 10 , Hala disclosed the device of claim 1 but does not explicitly state wherein completion of the invalidation request occurs in less than 1 millisecond. Jacobi discloses wherein completion of the invalidation request occurs in less than 1 millisecond. “The indicator is sent to the LSU 311 within a fixed maximum amount of time after the cache invalidation request is received from the coherency logic 312. The minimum amount of time from the cache invalidate request to the exclusive fetch data return use and the maximum amount of time from the cache invalidation request to the hit indication are accounted for such that any prefetched instructions following a store operation from the same store target line can be discarded . For example, if the minimum number of cycles from cache invalidate to exclusive fetch data return is 8 clock cycles, and prefetched instructions can be discarded following a store using the data return with an hit indication 2 cycles after the exclusive data return, then the maximum number of cycles from cache invalidate to hit indication is 10 cycles ” (Jacobi [0037] when the maximum cycle to invalidate is ten clock cycles, a chip running at over ten kHz would invalidate in under one millisecond ) It would have been obvious before the effective filing date of the invention to one of ordinary skill in the art to combine the teachings of knowing how long it would take for an invalidation request in Jacobi with the system in Hala. The motivation for doing so would be to improve the efficiency of the memory management by designing around the known parameters. Furthermore Jocobi discloses invalidation in a fixed amount of clock cycles, whereas the claim requires the invalidation to take less than 1 millisecond and therefore a POOSITA would look at the processor speed as a distinct design choice because the processor speed directly correlates to the frequency of clock cycles and does not affect or alter the underlying logic of the memory management system . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Moertl et al. (US 2008/0091855) discloses the use of ATC and storing entries corresponding to the untranslated memory address as well as invalidation of the entries by the root complex Chin et al. (US 2023/0176978) discloses the invalidation function using untranslated addresses and the entries of the lookup table that acts as an address translation cache being invalidated. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDNEY LI whose telephone number is (571)270-5967. The examiner can normally be reached Monday to Friday 10:00 AM to 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P Savla can be reached at (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.L./Examiner, Art Unit 2137 /Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137 Application/Control Number: 18/933,321 Page 2 Art Unit: 2137 Application/Control Number: 18/933,321 Page 3 Art Unit: 2137 Application/Control Number: 18/933,321 Page 4 Art Unit: 2137 Application/Control Number: 18/933,321 Page 5 Art Unit: 2137 Application/Control Number: 18/933,321 Page 8 Art Unit: 2137 Application/Control Number: 18/933,321 Page 9 Art Unit: 2137
Prosecution Insights