DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on May 22, 2026, in response to PTO Office Action mailed on February 24, 2026. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1-2, 6-7, 15, and 18 have been amended. Claim 5 has been cancelled. Claim 21 is a new claim. As a result, claims 1-4 and 6-21 are now pending in this application.
The objections to the drawings have been withdrawn due to the amendment filed May 22, 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on May 22, 2026, in response to PTO Office Action mailed on February 24, 2026, have been fully considered.
While the arguments pertaining to claims 1-4, 6-7, and 15-21 are persuasive, such arguments are not persuasive as they pertain to claims 8-14. While Applicant argues that the prior arts of record do not disclose a “bootloader,” further review of Michiels (Publication Number US 2025/0130946 A1) disclose the presence of “software stack” and “software components that run on general-purpose CPUs or GPUs” [Paragraphs 0022, 0029, and 0050]. Since Michiels broadly discloses the presence of “software” such an interpretation under broadest reasonable interpretation can also cover a bootloader.
Furthermore, Examiner notes that claims are given the broadest reasonable interpretation consistent with the specification (See In re Morris, 127 F.3d 1048, 44 USPQ2d 1023 (Fed. Cir. 1997). See MPEP § 2111 – § 2116.01 for case law pertinent to claim analysis). It is further rnoted that although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The limitations of claim 8 of “determine a transaction from the processor circuit is associated with a memory address included in the region of the off-chip memory” and “and direct the transaction to one of the off-chip memory or the internal memory based on whether the copy of the region of the off-chip memory to the internal memory has completed” can be interpreted as a system, based on information concerning a transaction, is directed to access the off-chip memory or the internal memory. However, unlike the other independent claims such as claim1 there is no direct correlation between a completion of the copy of a region of the off-chip memory to the internal memory resulting in accessing the internal memory (or otherwise accessing the off-chip memory if such completion is not done). Instead, accessing a particular memory regardless of the nature of the copy completion could still be a possible interpretation.
Allowable Subject Matter
Claims 1-4, 6-7, and 15-21 are allowed:
The following is an examiner’s statement of reason for allowance: Applicant's arguments filed on May 22, 2026, in response to PTO Office Action mailed on February 24, 2026, have been fully considered and are persuasive as they pertain to claims 1-4, 6-7, and 15-21. In particular, none of the prior arts of record discloses, alone or in combination, an accelerator circuit comprising: a direct memory access (DMA) circuit configured to copy contents of an off-chip memory (external to the device) to an internal memory of a device; and a decoder circuit configured to: determine a transaction from a processor circuit of the device is associated with a memory address included in a region of the off-chip memory to be copied to the internal memory; direct the transaction to one of the off-chip memory or the internal memory based on whether after a determination that a DMA copy of the region of the off-chip memory to the internal memory has completed, and direct the transaction to the off-chip memory after a determination that the DMA copy of the region of the off-chip memory to the internal memory has not completed.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Michiels (Publication Number US 2025/0130946 A1).
As per claim 8, Michiels discloses “A device comprising: internal memory (internal memory 120; FIG. 2).” Michiels discloses “a processor circuit (processor 110; FIG. 1).” Michiels discloses “and an accelerator circuit configured to: initiate a copy of a region of an off-chip memory to the internal memory based on configuration information provided by a bootloader (software stack or software running on CPUs or GPUs; Paragraphs 0022, 0029, and 0050), the bootloader stored in the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the processor circuit is associated with a memory address included in the region of the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the internal memory based on whether the copy of the region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache; [Paragraph 0017]. See also completion status in [Paragraph 0028]. Note the above limitation does could be interpreted as the system accessing the internal memory or external off-chip memory regardless of the condition of the copy completion).”
As per claim 9, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the processor circuit is a first processor circuit, the accelerator circuit is a first accelerator circuit, the region of the off-chip memory is a first region, the configuration information is first configuration information (see cache 240 with address table and the region occupied by data 202; FIG. 2), and including: a second processor circuit (processing device 502 represents one or more processors; Paragraph 0062).” Michiels discloses “and a second accelerator circuit configured to: initiate a copy of a second region of the off-chip memory to the internal memory based on second configuration information provided by the bootloader (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the second processor circuit is associated with a memory address included in the second region of the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the internal memory based on whether the copy of the second region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 10, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the processor circuit is a first processor circuit, the accelerator circuit is a first accelerator circuit, the internal memory is first internal memory, the region of the off-chip memory is a first region, the configuration information is first configuration information, and including: second internal memory (main memory 504 with instructions along with static memory 506 [FIG. 5]. Note the presence of one or more processors in [Paragraph 0062]).” Michiels discloses “a second processor circuit (processing device 502 represents one or more processors; Paragraph 0062).” Michiels discloses “and a second accelerator circuit configured to: initiate a copy of a second region of the off-chip memory to the second internal memory based on second configuration information provided by the bootloader (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the second processor circuit is associated with a memory address included in the second region of the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the second internal memory based on whether the copy of the second region of the off-chip memory to the second internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 11, Michiels discloses “The device of claim 10 (as disclosed by Michiels above), wherein the first internal memory includes a first tightly coupled memory associated with the first processor circuit, and the second internal memory includes a second tightly coupled memory associated with the second processor circuit (processing device 502 represents one or more processors [Paragraph 0062] in view of the processor with internal memory in [FIG. 1]).”
As per claim 12, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the accelerator circuit is configured to cause at least one of authentication or error correction to be performed on contents of the region of the off-chip memory copied to the internal memory (see error conditions; Paragraph 0028).”
As per claim 13, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the accelerator circuit is configured to: direct the transaction to the internal memory after a determination that the copy of the region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).” Michiels discloses “and direct the transaction to the off-chip memory after a determination that the copy of the region of the off-chip memory to the internal memory has not completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103(a) as being unpatentable over Michiels (Publication Number US 2025/0130946 A1) in view of Dowling (Patent Number US 6,128,728).
As per claim 14, Michiels discloses “The device of claim 13 (as disclosed by Michiels above).”
However, Michiels does not disclose the translation as disclosed in the limitation “wherein the accelerator circuit is configured to perform an address translation on the transaction before directing the transaction to the internal memory.”
Dowling discloses the translation as disclosed in the limitation “wherein the accelerator circuit is configured to perform an address translation on the transaction before directing the transaction to the internal memory (Column 21, lines 22-30).”
Michiels and Dowling are analogous art in that they in the field of memory system with external and internal memory.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Michiels and Dowling to provide for implementing a minimal number of register sets in a circularly buffered configuration to provide higher performance register shadowing and windowing systems at a fraction of the cost of prior art systems [Column 4, lines 4-14].
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach data transfer as they pertain to DMA transfers:
U.S. PATENT NUMBERS:
2013/0205298 A1 – [Paragraph 0027]
CONCLUDING REMARKS
Conclusions
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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/H.W.Y/Examiner, Art Unit 2181 July 21, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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