DETAILED ACTION
The instant application having Application No. 18/933,348 has a total of 20 claims pending in the application; there are 3 independent claims and 17 dependent claims, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
INFORMATION CONCERNING DRAWINGS
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 260 in FIG. 2; 945 in FIG. 9. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
INFORMATION CONCERNING THE SPECIFICATION
Specification
The applicant’s specification submitted is acceptable for examination purposes.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 8-13, and 15-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Michiels (Publication Number US 2025/0130946 A1).
As per claim 1, Michiels discloses “An accelerator circuit comprising: a direct memory access (DMA) circuit configured to copy contents of an off-chip memory to an internal memory of a device, the off-chip memory external to the device (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and a decoder circuit configured to: determine a transaction from a processor circuit of the device is associated with a memory address included in a region of the off-chip memory to be copied to the internal memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the internal memory based on whether a DMA copy of the region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 5, Michiels discloses “The accelerator circuit of claim 1 (as disclosed by Michiels above), wherein the decoder circuit is configured to: direct the transaction to the internal memory after a determination that the DMA copy of the region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).” Michiels discloses “and direct the transaction to the off-chip memory after a determination that the DMA copy of the region of the off-chip memory to the internal memory has not completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 8, Michiels discloses “A device comprising: internal memory (internal memory 120; FIG. 2).” Michiels discloses “a processor circuit (processor 110; FIG. 1).” Michiels discloses “and an accelerator circuit configured to: initiate a copy of a region of an off-chip memory to the internal memory based on configuration information provided by a bootloader, the bootloader stored in the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the processor circuit is associated with a memory address included in the region of the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the internal memory based on whether the copy of the region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache; [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 9, Michiels discloses “The device of claim 8 (as disclosed by *** above), wherein the processor circuit is a first processor circuit, the accelerator circuit is a first accelerator circuit, the region of the off-chip memory is a first region, the configuration information is first configuration information (see cache 240 with address table and the region occupied by data 202; FIG. 2), and including: a second processor circuit (processing device 502 represents one or more processors; Paragraph 0062).” Michiels discloses “and a second accelerator circuit configured to: initiate a copy of a second region of the off-chip memory to the internal memory based on second configuration information provided by the bootloader (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the second processor circuit is associated with a memory address included in the second region of the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the internal memory based on whether the copy of the second region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 10, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the processor circuit is a first processor circuit, the accelerator circuit is a first accelerator circuit, the internal memory is first internal memory, the region of the off-chip memory is a first region, the configuration information is first configuration information, and including: second internal memory (main memory 504 with instructions along with static memory 506 [FIG. 5]. Note the presence of one or more processors in [Paragraph 0062]).” Michiels discloses “a second processor circuit (processing device 502 represents one or more processors; Paragraph 0062).” Michiels discloses “and a second accelerator circuit configured to: initiate a copy of a second region of the off-chip memory to the second internal memory based on second configuration information provided by the bootloader (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the second processor circuit is associated with a memory address included in the second region of the off-chip memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the second internal memory based on whether the copy of the second region of the off-chip memory to the second internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 11, Michiels discloses “The device of claim 10 (as disclosed by Michiels above), wherein the first internal memory includes a first tightly coupled memory associated with the first processor circuit, and the second internal memory includes a second tightly coupled memory associated with the second processor circuit (processing device 502 represents one or more processors [Paragraph 0062] in view of the processor with internal memory in [FIG. 1]).”
As per claim 12, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the accelerator circuit is configured to cause at least one of authentication or error correction to be performed on contents of the region of the off-chip memory copied to the internal memory (see error conditions; Paragraph 0028).”
As per claim 13, Michiels discloses “The device of claim 8 (as disclosed by Michiels above), wherein the accelerator circuit is configured to: direct the transaction to the internal memory after a determination that the copy of the region of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).” Michiels discloses “and direct the transaction to the off-chip memory after a determination that the copy of the region of the off-chip memory to the internal memory has not completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
As per claim 15, Michiels discloses “A system comprising: random access memory (main memory 504; FIG. 5).” Michiels discloses “a processor circuit (processor 110; FIG. 1).” Michiels discloses “off-chip memory external to the processor circuit (external memory 130; FIG. 1).” Michiels discloses “and an accelerator circuit configured to: copy one or more regions of the off-chip memory to the random access memory based on configuration information provided by a bootloader (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the processor circuit is associated with a memory address included in a first one of the regions of the off-chip memory to be copied to the random access memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the random access memory based on whether the copy of the first one of the regions of the off-chip memory to the random access memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache; Paragraph 0017).”
As per claim 16, Michiels discloses “The system of claim 15 (as disclosed by Michiels above), wherein the processor circuit is a first processor circuit, the one or more regions of the off-chip memory are one or more first regions associated with the first processor circuit, and the off-chip memory includes one or more second regions associated with a second processor circuit (processing device 502 represents one or more processors [Paragraph 0062] in view of the processor with internal memory in [FIG. 1]).”
As per claim 17, Michiels discloses “The system of claim 16 (as disclosed by Michiels above), wherein the random access memory is first random access memory, the accelerator circuit is a first accelerator circuit, the configuration information is first configuration information, and including: second random access memory (main memory 504 with instructions along with static memory 506 [FIG. 5]. Note the presence of one or more processors in [Paragraph 0062]).” Michiels discloses “the second processor circuit (Note the presence of one or more processors in [Paragraph 0062]).” Michiels discloses “and a second accelerator circuit configured to: copy the one or more second regions of the off-chip memory to one of the first random access memory or the second random access memory based on second configuration information provided by the bootloader (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “determine a transaction from the second processor circuit is associated with a memory address included in a first one of the second regions of the off-chip memory to be copied to the one of the first random access memory or the second random access memory (a request to provide an application with a direct memory access to data stored at an external memory address of an external memory is received…the data is copied from the external memory address to a first internal memory address within the internal memory; Abstract, lines 1-6).” Michiels discloses “and direct the transaction to one of the off-chip memory or the one of the first random access memory or the second random access memory based on whether the copy of the first one of the second regions of the off-chip memory to the one of the first random access memory or the second random access memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache [Paragraph 0017]. See also completion status in [Paragraph 0028]).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 2-4, 6-7, and 14 are rejected under 35 U.S.C. 103(a) as being unpatentable over Michiels (Publication Number US 2025/0130946 A1) in view of Dowling (Patent Number US 6,128,728).
As per claim 2, Michiels discloses “The accelerator circuit of claim 1 (as disclosed by Michiels above), wherein the DMA circuit is configured to copy the region of the off-chip memory to the internal memory based on configuration information provided by a bootloader stored in the off-chip memory (Paragraphs 0017-0018).”
However, Michiels does not disclose the start address and end address as disclosed in the limitation “wherein the configuration information to specify a start address of the region of the off-chip memory and at least one of: an end address of the region of the off-chip memory, or a size of the region of the off-chip memory.”
Dowling discloses the start address and end address as disclosed in the limitation “wherein the configuration information to specify a start address of the region of the off-chip memory and at least one of: an end address of the region of the off-chip memory, or a size of the region of the off-chip memory (limit field could specify both a start and an end register address for move operations; Column 23, lines 39-50).”
Michiels and Dowling are analogous art in that they in the field of memory system with external and internal memory.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Michiels and Dowling to provide for implementing a minimal number of register sets in a circularly buffered configuration to provide higher performance register shadowing and windowing systems at a fraction of the cost of prior art systems [Column 4, lines 4-14].
As per claim 3, Dowling discloses “The accelerator circuit of claim 2 (as disclosed by Michiels and Dowling above), wherein the configuration information is to specify a start address of the internal memory to which the region of the off-chip memory is to be copied (limit field could specify both a start and an end register address for move operations).”
As per claim 4, Michiels discloses “The accelerator circuit of claim 2 (as disclosed by Michiels and Dowling above), wherein the region is one of a plurality of regions of the off-chip memory to be copied to the internal memory (Paragraphs 0017-0018).”
Michiels discloses “and cause the processor circuit to initiate execution of an application associated with the contents of the regions of the off-chip memory before the copying of the regions of the off-chip memory to the internal memory has completed (as it pertains to the presence of an external memory address registered in the cache [Paragraph 0016] or if the DMA controller determines that the external memory address is not registered in the cache; Paragraph 0017).”
Dowling discloses “the configuration information is to specify at least one of (i) respective start addresses and end addresses of the regions of the off-chip memory limit field could specify both a start and an end register address for move operations, or (ii) the respective start addresses and respective sizes of the regions of the off-chip memory (see the limit field of the descriptor; Column 20, lines 19-23), and execution of the bootloader by the processor circuit is to: cause the DMA circuit to initiate copying of the regions of the off-chip memory to the internal memory based on the configuration information (Column 20, lines 5-39; Column 23, lines 39-50).”
As per claim 6, Michiels discloses “The accelerator circuit of claim 5 (as disclosed by Michiels above).” However, Michiels does not disclose the translation as disclosed in the limitation “wherein the decoder circuit is configured to perform an address translation on the transaction before directing the transaction to the internal memory.”
Dowling discloses the translation as disclosed in the limitation “wherein the decoder circuit is configured to perform an address translation on the transaction before directing the transaction to the internal memory (Column 21, lines 22-30).”
Michiels and Dowling are analogous art in that they in the field of memory system with external and internal memory.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Michiels and Dowling to provide for implementing a minimal number of register sets in a circularly buffered configuration to provide higher performance register shadowing and windowing systems at a fraction of the cost of prior art systems [Column 4, lines 4-14].
As per claim 7, Michiels discloses “The accelerator circuit of claim 5 (as disclosed by Michiels above).” However, Michiels does not disclose the translation as disclosed in the limitation “wherein the decoder circuit is configured to perform an address translation on the transaction before directing the transaction to the off-chip memory.”
Dowling discloses the translation as disclosed in the limitation “wherein the decoder circuit is configured to perform an address translation on the transaction before directing the transaction to the off-chip memory (Column 21, lines 22-30).”
Michiels and Dowling are analogous art in that they in the field of memory system with external and internal memory.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Michiels and Dowling to provide for implementing a minimal number of register sets in a circularly buffered configuration to provide higher performance register shadowing and windowing systems at a fraction of the cost of prior art systems [Column 4, lines 4-14].
As per claim 14, Michiels discloses “The device of claim 13 (as disclosed by Michiels above).”
However, Michiels does not disclose the translation as disclosed in the limitation “wherein the accelerator circuit is configured to perform an address translation on the transaction before directing the transaction to the internal memory.”
Dowling discloses the translation as disclosed in the limitation “wherein the accelerator circuit is configured to perform an address translation on the transaction before directing the transaction to the internal memory (Column 21, lines 22-30).”
Michiels and Dowling are analogous art in that they in the field of memory system with external and internal memory.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Michiels and Dowling to provide for implementing a minimal number of register sets in a circularly buffered configuration to provide higher performance register shadowing and windowing systems at a fraction of the cost of prior art systems [Column 4, lines 4-14].
Claims 18-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Michiels (Publication Number US 2025/0130946 A1) in view of Yu (Publication Number US 2024/0211410 A1).
As per claim 18, Michiels discloses “The system of claim 15 (as disclosed by Michiels above).” However, Michiels does not disclose “further including a non-transitory computer-readable medium comprising computer readable instructions to cause a compute device to at least: profile program code based on test data to determine profile data,” “determine a call graph based on the program code and the profile data,” “order input sections of the program code based on a call graph,” “aggregate the input sections of program code into output sections based on annotations associated with the input sections of the program code, the annotations including region identifiers to identify the regions of the off-chip memory,” or “and place the output sections into the regions of the off-chip memory based on the region identifiers.”
Yu discloses “further including a non-transitory computer-readable medium comprising computer readable instructions to cause a compute device to at least: profile program code based on test data to determine profile data (as it pertains to modifying graphs; Paragraphs 0368-0370).” Yu discloses “determine a call graph based on the program code and the profile data (as it pertains to modifying graphs; Paragraphs 0368-0370).” Yu discloses “order input sections of the program code based on a call graph (as it pertains to modifying graphs; Paragraphs 0368-0370).” Yu discloses “aggregate the input sections of program code into output sections based on annotations associated with the input sections of the program code, the annotations including region identifiers to identify the regions of the off-chip memory (as it pertains to modifying graphs; Paragraphs 0368-0370).” Yu discloses “and place the output sections into the regions of the off-chip memory based on the region identifiers (as it pertains to modifying graphs; Paragraphs 0368-0370).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Michiels and Yu to enable quick processing of a large amount of data [Paragraph 0003].
As per claim 19, Yu discloses “The system of claim 18 (as disclosed by Michiels and Yu above), wherein the call graph is a second call graph, and the instructions are to cause the compute device to: determine a first call graph based on the program code (as it pertains to modifying graphs; Paragraphs 0368-0370).” Yu discloses “and prune the first call graph based on the profile data to determine the second call graph (as it pertains to modifying graphs; Paragraphs 0368-0370).”
As per claim 20, Yu discloses “The system of claim 19 (as disclosed by Michiels and Yu above), wherein the instructions are to cause the compute device to prune the first call graph based on at least one of function execution order or function execution frequency specified in the profile data (Paragraphs 0407-0408).”
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(c), the applicant's submission of the Information Disclosure Statement dated October 31, 2024; and May 7, 2025, is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach memory setups with internal and external components.
U.S. PATENT NUMBERS:2011/0016285 A1 – [Paragraph 0005]
2012/0254573 A1 – [Paragraphs 0027 and 0038]
CLOSING COMMENTS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS ALROBAYE can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.W.Y/Examiner, Art Unit 2181 February 20, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181