CTNF 18/933,921 CTNF 78593 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 and 9-18 of U.S. Patent No. 12,158,657. As to claim 1 of the current application, claim 1 of U.S. Patent No. 12,158,657 recites an array substrate comprising: a first substrate; a first metal layer, wherein the first metal layer is disposed above the first substrate; a second metal layer, wherein the second metal layer is disposed on a side of the first metal layer away from the first substrate; and a total reflection layer, wherein the total reflection layer is disposed as a whole on a side of the second metal layer away from the first substrate; wherein the array substrate at least further comprises a touch control unit, and the touch control unit is disposed on a side of the total reflection layer facing the first substrate; wherein the touch control unit comprises a first electromagnetic touch wire and a second electromagnetic touch wire arranged in different layers, the first electromagnetic touch wire and the second electromagnetic touch wire are arranged to intersect in a film thickness direction, and the first electromagnetic touch wire and the second electromagnetic touch wire are configured to obtain a touch position through electromagnetic touch positioning; and wherein the first metal layer is a gate layer, the second metal layer is a source and drain layer, the first electromagnetic touch wire and the gate layer are arranged in a same layer, and the second electromagnetic touch wire and the source and drain layer are arranged in a same layer. The patented claim does not recite wherein at least one side of the total reflection display panel comprises a chip disposing region, the first electromagnetic touch wire and the second electromagnetic touch wire are connected to one or more bonding chips in the chip disposing region. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the patented claim wherein at least one side of the total reflection display panel comprises a chip disposing region because it was a conventional structure (called chip-on-glass) which precluded the need for a flexible printed circuit board. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the patented claim wherein the first electromagnetic touch wire and the second electromagnetic touch wire are connected to one or more bonding chips in the chip disposing region in order to determine the position of user touch operations on the touch display panel. As to claim 2 of the current application, claim 9 of U.S. Patent No. 12,158,657 recites wherein the total reflection display panel further comprises a sub-pixel unit, a color resist unit disposed on a side of the sub-pixel unit away from the first substrate, and a ratio of an area of the color resist unit to an area of the sub-pixel unit is less than or equal to 1:2 in the film thickness direction. As to claim 3 of the current application, claim 10 of U.S. Patent No. 12,158,657 recites wherein at least one side of the total reflection display panel comprises a chip disposing region, and the chip disposing region comprises a central region and an edge region located outside the central region, the edge region is provided with a bonding chip, the first electromagnetic touch wire or the second electromagnetic touch wire is respectively connected to the bonding chip in the edge region, and the first electromagnetic touch wire or the second electromagnetic touch wire are arranged symmetrically with respect to the central region. As to claim 4 of the current application, claim 11 of U.S. Patent No. 12,158,657 recites wherein at least one side of the total reflection display panel comprises a chip disposing region, and the chip disposing region comprises a central region and an edge region located outside the central region, and the first electromagnetic touch wire and the second electromagnetic touch wire are respectively connected to different bonding chips. As to claim 5 of the current application, claim 12 of U.S. Patent No. 12,158,657 recites wherein the first electromagnetic touch wire is connected to the bonding chip in the edge region, and the second electromagnetic touch wire is connected to the bonding chip in the central region. As to claim 6 of the current application, claim 13 of U.S. Patent No. 12,158,657 recites wherein the first electromagnetic touch wire is connected to six outermost ones of bonding chips at an end of the chip disposing region. As to claim 7 of the current application, claim 14 of U.S. Patent No. 12,158,657 recites wherein bonding chips are arranged in an array, when first electromagnetic touch wires or second electromagnetic touch wires are arranged at equal intervals. As to claim 8 of the current application, claim 15 of U.S. Patent No. 12,158,657 recites wherein at least one side of the total reflection display panel comprises a chip disposing region, and the chip disposing region comprises a central region and an edge region located outside the central region, the first electromagnetic touch wire and the second electromagnetic touch wire are connected to a same bonding chip, the bonding chip comprises a plurality of pins, and the plurality of pins are connected to the first electromagnetic touch wire or the second electromagnetic touch wire in a one-to-one correspondence. As to claim 9 of the current application, claim 16 of U.S. Patent No. 12,158,657 recites wherein the total reflection display panel is further provided with an optical compensation layer for increasing a viewing angle of light, the optical compensation layer is provided on a side of the total reflection layer away from the first substrate. As to claim 10 of the current application, claim 17 of U.S. Patent No. 12,158,657 recites wherein the optical compensation layer is a lens or a prism capable of diffusing light. As to claim 11 of the current application, claim 18 of U.S. Patent No. 12,158,657 recites wherein the optical compensation layer further comprises a first optical compensation layer and a second optical compensation layer disposed on a surface of a side of the first optical compensation layer away from the first substrate, and a refractive index of the first optical compensation layer is greater than a refractive index of the second optical compensation layer. As to claim 12 of the current application, claim 2 of U.S. Patent No. 12,158,657 recites wherein adjacent ones of first electromagnetic touch wires are arranged in parallel to each other and adjacent ones of second electromagnetic touch wires are arranged in parallel to each other. As to claim 13 of the current application, claim 3 of U.S. Patent No. 12,158,657 recites wherein the gate layer comprises a gate, and the first electromagnetic touch wire and the gate are spaced apart from each other. As to claim 14 of the current application, claim 4 of U.S. Patent No. 12,158,657 recites wherein the source and drain layer comprises a source and a drain, and the second electromagnetic touch wire is arranged spaced apart from the source and spaced apart from the drain. As to claim 15 of the current application, claim 5 of U.S. Patent No. 12,158,657 recites wherein the gate layer further comprises a scan line arranged along a first direction, the source and drain layer comprise a data line arranged along a second direction, the first electromagnetic touch wire is arranged along the first direction, the second electromagnetic touch wire is arranged along the second direction, and the first electromagnetic touch wire and the second electromagnetic touch wire are perpendicular to each other in the film thickness direction. As to claim 16 of the current application, claim 6 of U.S. Patent No. 12,158,657 recites wherein the source and drain layer comprises a source and a drain, and the source and the drain are disposed on a same side of the second electromagnetic touch wire. As to claim 17 of the current application, claim 7 of U.S. Patent No. 12,158,657 recites wherein at least three of the first electromagnetic touch wires form a first loop, and the first electromagnetic touch wires form a plurality of the first loops, at least three of the second electromagnetic touch wires form a second loop, and the second electromagnetic touch wires form a plurality of the second loops. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Chung whose telephone number is (571)272-2288. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at (571)272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID Y CHUNG/Primary Examiner, Art Unit 2871 Application/Control Number: 18/933,921 Page 2 Art Unit: 2871 Application/Control Number: 18/933,921 Page 3 Art Unit: 2871 Application/Control Number: 18/933,921 Page 4 Art Unit: 2871 Application/Control Number: 18/933,921 Page 5 Art Unit: 2871 Application/Control Number: 18/933,921 Page 6 Art Unit: 2871 Application/Control Number: 18/933,921 Page 7 Art Unit: 2871
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