DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claim 1:
The “selecting” step, as drafted, is a process that, under its broadest reasonable interpretation, covers a mathematical calculation but for the recitation of generic computer components. That is, other than reciting a “processing device…to perform operations” nothing in the claim precludes the step from practically being calculated mathematically. If a claim limitation, under its broadest reasonable interpretation, covers a mathematical calculation but for the recitation of generic computer components, then it falls within the “Mathematical Concept” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of a “memory device”, “processing device”, “receiving” step, and “writing” step. The “memory device” and “processing device” are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using generic computer components (see MPEP 2106.05(f)). Additionally, the “receiving” step and “writing” step amount to no more than mere data gathering and output which is insignificant extra-solution activity (see MPEP 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of a “memory device” and “processing device” are generic computer components recited at a high level of generality amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Additionally, the “receiving” step is “receiving or transmitting data over a network” which the courts have found to be a well-understood, routine, and conventional activity (see MPEP 2106.05(d)(II)(i)). Lastly, the “writing” step is “storing and retrieving information in memory” which the courts have found to be a well-understood, routine, and conventional activity (see MPEP 2106.05(d)(II)(iv)). The claim is not patent eligible.
As per claim 8:
The “selecting” step, as drafted, is a process that, under its broadest reasonable interpretation, covers a mathematical calculation but for the recitation of generic computer components. Nothing in the claim precludes the step from practically being calculated mathematically. If a claim limitation, under its broadest reasonable interpretation, covers a mathematical calculation but for the recitation of generic computer components, then it falls within the “Mathematical Concept” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of a “memory device”, “receiving” step, and “writing” step. The “memory device” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using generic computer components (see MPEP 2106.05(f)). Additionally, the “receiving” step and “writing” step amount to no more than mere data gathering and output which is insignificant extra-solution activity (see MPEP 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of a “memory device” is a generic computer component recited at a high level of generality amounts to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Additionally, the “receiving” step is “receiving or transmitting data over a network” which the courts have found to be a well-understood, routine, and conventional activity (see MPEP 2106.05(d)(II)(i)). Lastly, the “writing” step is “storing and retrieving information in memory” which the courts have found to be a well-understood, routine, and conventional activity (see MPEP 2106.05(d)(II)(iv)). The claim is not patent eligible.
As per claim 15:
The “selecting” step, as drafted, is a process that, under its broadest reasonable interpretation, covers a mathematical calculation but for the recitation of generic computer components. That is, other than reciting a “processing device to perform operations” nothing in the claim precludes the step from practically being calculated mathematically. If a claim limitation, under its broadest reasonable interpretation, covers a mathematical calculation but for the recitation of generic computer components, then it falls within the “Mathematical Concept” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of a “non-transitory machine-readable medium”, “memory device”, “processing device”, “receiving” step, and “writing” step. The “memory device” and “processing device” are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using generic computer components (see MPEP 2106.05(f)). Additionally, the “receiving” step and “writing” step amount to no more than mere data gathering and output which is insignificant extra-solution activity (see MPEP 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of a “non-transitory machine-readable medium”, “memory device”, and “processing device” are generic computer components recited at a high level of generality amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using generic computer components cannot provide an inventive concept. Additionally, the “receiving” step is “receiving or transmitting data over a network” which the courts have found to be a well-understood, routine, and conventional activity (see MPEP 2106.05(d)(II)(i)). Lastly, the “writing” step is “storing and retrieving information in memory” which the courts have found to be a well-understood, routine, and conventional activity (see MPEP 2106.05(d)(II)(iv)). The claim is not patent eligible.
For claims 2-7, 9-14 and 16-20:
The further claimed limitations neither integrate the judicial exception into a practical application nor sufficient to mount to significantly more than the judicial exception. This is because the further claimed limitations only further define certain characteristics of the generic computer components, which limits the claims to a certain field of use and technological environment (see MPEP 2106.05(h).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,169,629. Although the claims at issue are not identical, they are not patentably distinct from each other because the patent claims [cited as line numbers in parentheses] teaches the instant claims as flows:
As per claim 1:
The patent claim 1 teaches system comprising: a memory device [lines 1-2]; and a processing device, operatively coupled to the memory device, to perform operations comprising [lines 3-4]: receiving a request to write data to the memory device [lines 14-15]; responsive to receiving the request to write data, selecting a first memory block from a plurality of erased candidate memory blocks of the memory device in accordance with respective erase depth levels of each of the plurality of erased candidate memory blocks [lines 16-20].
The patent claim 1, however, does not recite the operation of “writing the data to the first memory block”.
Claim 12 teaches the operation of “writing the data to the first block [lines 3-4].
It would have been obvious to one having ordinary skill in the art to come up with the system of claim 1 using the teaching of patent claims 1 and 12. Clearly, the first block is selected for the purpose of writing the data responsive to the write request.
For claims 2-20:
The claimed limitations of claims 2-20 can also be found in the patent claims 1-20.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-8 , 14-15 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Langlois et al., US 2010/0037001 [herein Langlois].
As for claims 1, 8 and 15:
Langlois teaches a system [figure 1] comprising: a memory device [e.g., memory device 112]; and a processing device [e.g., processor 104] , operatively coupled to the memory device, to perform operations comprising:
receiving a request to write data to the memory device; responsive to receiving the request to write data, selecting a first memory block from a plurality of erased candidate memory blocks of the memory device in accordance with respective erase depth levels of each of the plurality of erased candidate memory blocks; and writing the data to the first memory block [see para. 0051; figure 6, steps 602-606; block with minimum erase count value (i.e., erase depth level) is selected for writing responsive to a write request].
For claims 7, 14 and 20:
The further claimed limitation of “wherein the first memory block is selected from a plurality of erased candidate memory blocks in an order based on the respective erase depth levels of the plurality of erased candidate memory blocks, wherein the order is from a shallowest erase depth level to a deepest erase depth level” is also implicitly taught by Langlois. This is because the block with minimum erase count value is selected first writing responsive to a write request [see again para. 0051, figure 6, steps 602-606]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 9-12 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Langlois in view of Hung et al., US 2022/0137842 [hereinafter, Hung].
For claims 2, 9 and 16:
Langlois teaches a system as mentioned above.
Langlois, however, does not disclose that “wherein the respective erase depth levels are associated with respective threshold criteria, and wherein the respective threshold criteria associated with the respective erase depth levels are satisfied by one or more block characteristics of the first memory block.
Hung teaches associating erase counts with ranges (i.e., erase depth levels). Each of the erase count range associated with erase count (i.e., block characteristic) thresholds [see para. 0033 (e.g., range A include erase counts from 0-100)].
It would have been obvious to one having ordinary skill in the art, prior to the effective filing date of eh claimed invention, to configure the Langlois system to associate the erase counts with ranges, as taught by Hung. The ability to characterize memory block using erase count ranges would be to motivation for doing so in the Langlois system.
For claims 3, 10 and 17:
The further claimed limitation of “wherein the respective threshold criteria associated with the respective erase depth levels comprise a respective range of values, and wherein the respective threshold criteria associated with the respective erase depth levels are satisfied if each of the one or more block characteristics of the first memory block is in the respective range of values” is also taught by Hung. This is because each erase count ranges are associated with a particular block erase counts [see again para. 0033].
For claims 4, 11 and 18:
The further claimed limitation of “wherein the one or more block characteristics of the first memory block include a program erase count of the first memory block” is also taught by Langlois [see again para. 0051; figure 6, steps 602-606; block with minimum erase count value (i.e., erase depth level) is selected for writing responsive to a write request .
For claims 5, 12 and 19:
The further claimed limitation of “wherein the respective threshold criteria associated with the respective erase depth levels includes a respective program erase count criterion that is satisfied if the program erase count of the first memory block is in a respective range of values included in the respective program erase count criteria” is also taught by Hung through erase count ranges. [see again para. 0033].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Golov, US 2022/0129394, teaches selecting the block with the lowest erase count for eh next write [see para. 0063].
Kanno, US 2017/0262228, teaches selecting block having minimum erase count as a write target block [see para. 0325].
Di Sena et al., US 2006/0155917, teaches that free block with lowest erase count is selected for data writing [see para. 0020].
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/HIEP T NGUYEN/ Primary Examiner, Art Unit 2137