Prosecution Insights
Last updated: October 02, 2026
Application No. 18/934,016

Heterogeneous Multi-Channel Scanning for Wireless Devices

Non-Final OA §102§103
Filed
Oct 31, 2024
Examiner
WELTE, BENJAMIN PETER
Art Unit
2477
Tech Center
2400 — Computer Networks
Assignee
Avago Technologies International Sales Pte. Limited
OA Round
1 (Non-Final)
64%
Grant Probability
Moderate
1-2
OA Rounds
1y 3m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allowance Rate
28 granted / 44 resolved
+5.6% vs TC avg
Moderate +15% lift
Without
With
+14.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
31 currently pending
Career history
93
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
79.7%
+39.7% vs TC avg
§102
17.4%
-22.6% vs TC avg
§112
1.7%
-38.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 44 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1-20 are objected to because of their line numbering which confuses the numbering of the claims themselves. Also, Claim 20 is objected to because it recites “detecting energy the channel” which presumably was intended to mean “detecting energy on the channel”. Allowable Subject Matter Claim 11 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not fairly teach “determining one or more arrival windows for the first channel based on estimated times of arrival of one or more subsequent beacons” and “deprioritizing the first channel during the one or more arrival windows” in combination with the other limitations of these claims. Other prior art, e.g. Patil et al. (US 2018/0110046 A1), does describe rescheduling subsequent beacon transmissions to prevent future collisions, but it does not describe prioritizing one beacon channel over another. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 9-10, and 13 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Su et al. (US 2026/0136360 A1, hereinafter “Su”). As to Claims 1 and 13: Su describes a method to receive and demodulate multiple signals simultaneously using parallel neural networks. Specifically, Su teaches: A wireless device comprising a multi-scan PHY block Fig. 8 in Su depicts “ESN #2”, which can receive and demodulate a “256QAM received signal” and a “1024QAM received signal” in parallel. M front-end blocks, each comprising logic to detect modulated signals on each of a plurality of channels The blocks in “ESN #2” in Fig. 8 that each disassemble a signal into a “real part” and “imaginary parts” map to “M front-end blocks, each comprising logic to detect modulated signals on each of a plurality of channels”. N back-end blocks, each comprising logic to demodulate a signal modulated with a respective modulation The neural network in Fig. 8 that receives the “real part” and “imaginary part” of both the “256 QAM received signal” and “1024 QAM received signal” maps to “N back-end blocks, each comprising logic to demodulate a signal modulated with a respective modulation”. M and N are integers, and M is greater than N In Fig. 8 in Su, M is 2 and N is 1, both integer values. A PHY controller comprising logic to manage communications between the front-end blocks and the back-end blocks Fig. 9 in Su shows a “Controller 910” coupled to the “Transceiver 920” which is “configured to perform the above method mentioned” (Su, 0206). The controller qualifies as a “PHY controller” because the signal’s deconstruction into real and imaginary parts in Fig. 8 shows that the transceiver operates on the level of the physical layer. Claim 13 encompasses the same subject matter as Claim 1 in the form of a method claim. As to Claim 9: Su teaches: Logic to receive, from a first front-end block, an indication of a signal having a first modulation Su describes “determining the structure of the neural network” in Fig. 7 “based on ... the modulation scheme configured to the downlink transmission” (Su, 0190). Here, “determining the structure of the neural network based on ... the modulation scheme” demonstrates that the neural network logic includes “logic to receive, from a first front-end block, an indication of a signal having a first modulation”. Logic to assign, based at least in part on the indication, the first front-end block to a first back-end block configured to receive signals having the first modulation Su describes “determining the structure of the neural network” in Fig. 7 “based on ... the modulation scheme configured to the downlink transmission” (Su, 0190). Here, “determining the structure of the neural network based on ... modulation scheme” demonstrates that there is “logic to assign, based at least in part on the indication, the first front-end block to a first back-end block configured to receive signals having the first modulation”. As to Claim 10: Su teaches: Detecting signals on two or more channels Su describes “determining the number of neural networks” in Fig. 7 “based on at least one of the number of users with uplink transmissions on a same time unit” (Su, 0182). Here, “users with uplink transmissions on a same time unit” map to “detecting signals on two or more channels”. Handling a demodulation contention resulting from detected signals Su describes “determining the number of neural networks” in Fig. 7 “based on at least one of the number of users with uplink transmissions on a same time unit” (Su, 0182). Here, the creation of multiple “neural networks” to receive “uplink transmissions on a same time unit” maps to “handling a demodulation contention resulting from detected signals”. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (2026/0136360 A1) in view of Zarubica et al. (US 2023/0112645 A1, hereinafter “Zarubica”). As to Claims 2 and 14: Su teaches: Each of the front-end blocks comprises: at least one packet detector; and The blocks in Fig. 8 of Su that disassemble the signal into a “real part” and an “imaginary part” each correspond to a “packet detector”. A front-end controller comprising logic to manage operation of that front-end block The “Controller 910” in Fig. 9 of Su maps to “a front-end controller comprising logic to manage operation of that front-end block”. Su does not explicitly disclose: The PHY block further comprises: J energy detectors J and M are integers, and J is greater than or equal to M; and Directing operation of the respective front-end block, based on information about energy detected by one or more of the energy detectors However, Zarubica does describe methods to receive over multiple frequencies simultaneously. Specifically, Zarubica teaches: The PHY block further comprises: J energy detectors Zarubica describes a “STEP message” that uses “two receive band simultaneously” based on “detect[ing] the power within the frequency spectrum” (Zarubica, 0048). Here, “detect[ing] the power within the frequency spectrum” evinces the presence of “J energy detectors” (Zarubica, 0048). J and M are integers, and J is greater than or equal to M Zarubica’s description of “detect[ing] the power within the frequency spectrum over both receive bands simultaneously” (Zarubica, 0048) shows that “J and M are integers, and J is greater than or equal to M” because energy detection occurs for each receiving band, indicating that J and M are equal. Directing operation of the respective front-end block, based on information about energy detected by one or more of the energy detectors Zarubica describes “detect[ing] the power within the frequency spectrum over both receive band simultaneously” to detect packets (Zarubica, 0048). Here, packet detection based on “the power within the frequency spectrum” maps to “directing operation of the respective front-end block, based on information about energy detected by one or more of the energy detectors”. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Zarubica’s method of detecting packets based on energy into Su’s method for decoding several MCSs simultaneously. As Zarubica explains, this “provides a means to allow the network to perform both intra-band and inter-band frequency agility in the presence of interference (e.g., jamming)” (Zarubica, 0048). Claim 14 encompasses the same subject matter as Claim 2 in the form of a method claim. As to Claim 3: Su does not explicitly disclose: J is equal to M; and Each of the front-end blocks comprises a respective one of the energy detectors However, Zarubica does teach: J is equal to M Zarubica’s description of “detect[ing] the power within the frequency spectrum over both receive bands simultaneously” (Zarubica, 0048) shows that “J is equal to M” because energy detection occurs for each receiving band. Each of the front-end blocks comprises a respective one of the energy detectors Zarubica’s description of “detect[ing] the power within the frequency spectrum over both receive bands simultaneously” (Zarubica, 0048) shows that “J is equal to M” because energy detection occurs for each receiving band. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Zarubica’s method of detecting packets based on energy into Su’s method for decoding several MCSs simultaneously. As Zarubica explains, this “provides a means to allow the network to perform both intra-band and inter-band frequency agility in the presence of interference (e.g., jamming)” (Zarubica, 0048). As to Claim 4: Su teaches: Logic to compute a likelihood that a preamble of a packet received on a particular channel has a particular modulation In describing the neural network in “ESN #2” in Fig. 8, Su states that “[a]fter determining the structure of the neural network based on the transmission configuration parameter(s), the neural network with the determined structure may be used to perform the non-linear compensation for the multiple second signals” (Su, 0201). Here, “determining the structure of the neural network” maps to “logic to compute a likelihood that a preamble of a packet received on a particular channel has a particular modulation” since the structure of the neural network corresponds to a particular modulation. Logic to detect a modulation of the packet based at least in part on the likelihood The neural network in “ESN #2” in Fig. 8 of Su maps to “logic to detect a modulation of the packet based at least in part on the likelihood”. Logic to bias detection of the modulation toward the particular modulation In describing the neural network in “ESN #2” in Fig. 8, Su states that “[a]fter determining the structure of the neural network based on the transmission configuration parameter(s), the neural network with the determined structure may be used to perform the non-linear compensation for the multiple second signals” (Su, 0201). Here, the resulting “structure of the neural network” maps to “logic to bias detection of the modulation toward the particular modulation” since the structure of the neural network is tailored to detect a particular modulation. As to Claim 5: Su does not explicitly disclose: Each of the energy detectors comprises logic to generate information about signals received on a channel to which that energy detector is tuned The PHY controller further comprises logic to generate channel occupancy information about one or more channels based on the information about signals received on the one or more channels However, Zarubica does teach: Each of the energy detectors comprises logic to generate information about signals received on a channel to which that energy detector is tuned Zarubica describes “detect[ing] the power within the frequency spectrum over both receive bands simultaneously” which a device uses to “determine a predicted SNR condition for each frequency bin in each receive band of the network” (Zarubica, 0048, 0050). Here, “a predicted SRN condition” maps to “information about signals received on a channel to which that energy detector is tuned”. The PHY controller further comprises logic to generate channel occupancy information about one or more channels based on the information about signals received on the one or more channels Zarubica describes “detect[ing] the power within the frequency spectrum over both receive bands simultaneously” which a device uses to “determine a predicted SNR condition for each frequency bin in each receive band of the network” (Zarubica, 0048, 0050). Here, “a predicted SRN condition” maps to “channel occupancy information about one or more channels based on the information about signals received on the one or more channels”. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Zarubica’s method of detecting packets based on energy into Su’s method for decoding several MCSs simultaneously. As Zarubica explains, this “provides a means to allow the network to perform both intra-band and inter-band frequency agility in the presence of interference (e.g., jamming)” (Zarubica, 0048). Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2026/0136360 A1) in view of Aldaz et al. (US 2008/0165780 A1, hereinafter “Aldaz”). As to Claim 6: Su does not explicitly disclose: A packet filter However, Aldaz does describe a method to filter packets at the MAC layer. Specifically, Aldaz teaches: A packet filter Aldaz describes “filtering out [a] packet” if “it is determined that the packet is not a beacon packet” in step 756 of Fig. 7C (Aldaz, 0092). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Aldaz’s practice of packet filtering into Su’s method for detecting multiple simultaneous signals with different MCSs. As Aldaz explains, this can help “perform[] real-time reassembly” of “VoIP traffic” (Aldaz, 0093). As to Claim 8: Su teaches: Demodulating the modulated signal recovers a transmitted frame from a wireless packet Fig. 2B in Su shows a “reception path 250” which includes “demodulation block 280” for “demodulat[ing] and decod[ing] the modulated symbols to recover the original input data stream” (Su, 0062, 0065). Here, “the original input data stream” corresponds to “a transmitted frame from a wireless packet” Su does not explicitly disclose: Logic to identify a set of data associated with the recovered frame One or more tags in the recovered frame; or at least a portion of one or more fields from the recovered frame Logic to determine, based on the identified set of data, whether to forward the recovered frame to a MAC interface However, Aldaz does teach: Logic to identify a set of data associated with the recovered frame Fig. 7B in Aldaz shows the process of decoding a received packet which includes Step 736: “Decod[ing] at least a header portion of the packet at a physical layer device”. Here, “a header portion of the packet” maps to “a set of data associated with the recovered frame”. One or more tags in the recovered frame; or at least a portion of one or more fields from the recovered frame Fig. 7B in Aldaz desecribes recovering “a header portion of the packet” in step 736 including “a destination medium access control (MAC) address”. Logic to determine, based on the identified set of data, whether to forward the recovered frame to a MAC interface Step 740 in Fig. 2B determines whether to “Deactivate the MAC address parser” in step 741 or “activate a MAC device for performing data processing functions 744”. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Aldaz’s practice of packet filtering into Su’s method for detecting multiple simultaneous signals with different MCSs. As Aldaz explains, this can help “perform[] real-time reassembly” of “VoIP traffic” (Aldaz, 0093). Claim(s) 7, 15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2026/0136360 A1) in view of Garlapati et al. (US 11,496,243 B1, hereinafter “Garlapati”). As to Claims 7 and 15: Su teaches: Logic to demodulate the signal bit-by-bit Su describes a “received signal” that “undergoes demodulation and decoding in turn to obtain required data bits” (Su, 0093). Su does not explicitly disclose: Logic to evaluate, while demodulating the signal, one or more demodulated bits against one or more bitmask conditions Logic to determine, based on an evaluation of the one or more demodulated bits against the one or more bitmask conditions, whether to terminate demodulation of the signal before demodulating an entire wireless packet, based at least in part on whether the one or more demodulated bits satisfies one or more termination conditions However, Garlapati does describe a method to prematurely end decoding based on a cyclic redundancy check. Specifically, Garlapati teaches: Logic to evaluate, while demodulating the signal, one or more demodulated bits against one or more bitmask conditions Garlapati states that a “code block type may be associated with a first number of decoding cycles, where a code block may be early terminated based at least in part on a traditional implementation of a 16-bit RNTI masking” (Garlapati col. 26, lines 41-44). Logic to determine, based on an evaluation of the one or more demodulated bits against the one or more bitmask conditions, whether to terminate demodulation of the signal before demodulating an entire wireless packet, based at least in part on whether the one or more demodulated bits satisfies one or more termination conditions Garlapati states that a “code block type may be associated with a first number of decoding cycles, where a code block may be early terminated based at least in part on a traditional implementation of a 16-bit RNTI masking” (Garlapati col. 26, lines 41-44). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Garlapati’s method for terminating decoding of a code block early into Su’s method for demodulating two signals simultaneously. As Garlapati states, this “may result in decoding cycle savings” for “two different types of code blocks” (Garlapati, col. 26, lines 53-55). Claim 15 encompasses the same limitations in the form of a method claim that additionally requires that: Each of the back-end blocks comprises a packet filter Garlapati describes “CRC masking” used for “decoding ... code blocks” (Garlapati, col. 26, lines 44-55). As to Claim 20: Su teaches: A multi-scan PHY block of a wireless device Fig. 8 in Su depicts “ESN #2”, which can receive and demodulate a “256QAM received signal” and a “1024QAM received signal” in parallel. M front-end blocks, each comprising: a detector comprising logic to detect signals on each of a plurality of channels The blocks in “ESN #2” in Fig. 8 that each disassemble a signal into a “real part” and “imaginary parts” map to “M front-end blocks, each comprising logic to detect modulated signals on each of a plurality of channels”. Detecting energy the channel; and sensing, in response to detecting energy on the channel, a modulation of a carrier signal on the channel Su describes determining the “modulation scheme allocated to the uplink transmission” based on the “modulation order” for “256QAM” and “1024QAM” (Su, 0133). Here, “modulation order” is analogous to “energy” since a higher modulation order will require more energy. N back-end blocks, each comprising: a packet filter; and logic to demodulate a signal modulated having one of a the plurality of modulations The neural network in Fig. 8 that receives the “real part” and “imaginary part” of both the “256 QAM received signal” and “1024 QAM received signal” maps to “N back-end blocks, each comprising logic to demodulate a signal modulated with a respective modulation”. Demodulating the signal bit-by-bit Su describes a “received signal” that “undergoes demodulation and decoding in turn to obtain required data bits” (Su, 0093). A PHY controller comprising logic to manage communications between the front-end blocks and the back-end blocks Fig. 9 in Su shows a “Controller 910” coupled to the “Transceiver 920” which is “configured to perform the above method mentioned” (Su, 0206). The controller qualifies as a “PHY controller” because the signal’s deconstruction into real and imaginary parts in Fig. 8 shows that the transceiver operates on the level of the physical layer. Logic to receive, from a first front-end block, an indication of a signal having a first modulation Su describes “determining the structure of the neural network” in Fig. 7 “based on ... the modulation scheme configured to the downlink transmission” (Su, 0190). Here, “determining the structure of the neural network based on ... the modulation scheme” demonstrates that the neural network logic includes “logic to receive, from a first front-end block, an indication of a signal having a first modulation”. Logic to assign, based at least in part on the indication, the first front-end block to a first back-end block configured to receive signals having the first modulation Su describes “determining the structure of the neural network” in Fig. 7 “based on ... the modulation scheme configured to the downlink transmission” (Su, 0190). Here, “determining the structure of the neural network based on ... modulation scheme” demonstrates that there is “logic to assign, based at least in part on the indication, the first front-end block to a first back-end block configured to receive signals having the first modulation”. M and N are integers, and M is greater than N In Fig. 8 in Su, M is 2 and N is 1, both integer values. Su does not explicitly disclose: Evaluating, while demodulating the signal, one or more demodulated bits against one or more bitmask conditions Logic to determine, based on an evaluation of the one or more demodulated bits against the one or more bitmask conditions, whether to terminate demodulation of the signal before demodulating an entire frame However, Garlapati does teach: Evaluating, while demodulating the signal, one or more demodulated bits against one or more bitmask conditions Garlapati states that a “code block type may be associated with a first number of decoding cycles, where a code block may be early terminated based at least in part on a traditional implementation of a 16-bit RNTI masking” (Garlapati col. 26, lines 41-44). Logic to determine, based on an evaluation of the one or more demodulated bits against the one or more bitmask conditions, whether to terminate demodulation of the signal before demodulating an entire frame Garlapati states that a “code block type may be associated with a first number of decoding cycles, where a code block may be early terminated based at least in part on a traditional implementation of a 16-bit RNTI masking” (Garlapati col. 26, lines 41-44). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Garlapati’s method for terminating decoding of a code block early into Su’s method for demodulating two signals simultaneously. As Garlapati states, this “may result in decoding cycle savings” for “two different types of code blocks” (Garlapati, col. 26, lines 53-55). Claim 15 encompasses the same limitations in the form of a method claim that additionally requires that: Each of the back-end blocks comprises a packet filter Garlapati describes “CRC masking” used for “decoding ... code blocks” (Garlapati, col. 26, lines 44-55). Claim(s) 12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2026/0136360 A1) in view of Wei et al. (US 2005/0002444 A1, hereinafter “Wei”). As to Claims 12 and 19: Su does not explicitly disclose: Causing a back-end block to demodulate a first signal Storing a second one or more signals in a buffer while the back-end block demodulates the first overlapping signal Causing the back-end block to demodulate the second one or more signals after the back-end block has demodulated the first signal However, Wei does describe a method to demodulate a pilot signal received simultaneously with multiple other signals that need to be demodulated. Specifically, Wei teaches: Causing a back-end block to demodulate a first signal Wei describes a “receiver” that receives “data and rate indicator frames ... concurrent[ly]” and “at first only demodulates the rate indicator modulation symbols” (Wei, 0058). Storing a second one or more signals in a buffer while the back-end block demodulates the first overlapping signal Wei describes a “receiver” that receives “data and rate indicator frames ... concurrent[ly]” and “[t]he data channel, pilot channel, and rate indicator channel are all stored in a buffer” while “at first only demodulates the rate indicator modulation symbols” (Wei, 0058). Here, the “data channel ... stored in a buffer” corresponds to “storing a second one or more signals in a buffer”, and “at first only demodulat[ing] the rate indicator modulation symbols” maps to “while the back-end block demodulates the first overlapping signal”. Causing the back-end block to demodulate the second one or more signals after the back-end block has demodulated the first signal Wei teaches that “[t]he stored signals are then processed by the multi-path receiver” after “the receiver at first only demodulates the rate indicator modulation symbols” (Wei, 0058). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Wei’s method for buffering a signal to demodulate it later into Su’s method for receiving concurrent signals. As Wei points out, this allows simultaneous reception using channels with different data rates (Wei, 0012). Claim 19 encompasses the same subject matter as Claim 12 in the form of a method claim. Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 2026/0136360 A1) in view of Garlapati (US 11,496,243 B1) and further in view of Aldaz et al. (US 2008/0165780 A1). As to Claim 16: Su teaches: Demodulating the modulated signal recovers a transmitted frame from a wireless packet Fig. 2B in Su shows a “reception path 250” which includes “demodulation block 280” for “demodulat[ing] and decod[ing] the modulated symbols to recover the original input data stream” (Su, 0062, 0065). Here, “the original input data stream” corresponds to “a transmitted frame from a wireless packet” Su does not explicitly disclose: Identifying a set of data associated with the recovered frame One or more tags in the recovered frame; or at least a portion of one or more fields from the recovered frame Determining, based on the identified set of data, whether to forward the recovered frame to a MAC interface However, Aldaz does teach: Identifying a set of data associated with the recovered frame Fig. 7B in Aldaz shows the process of decoding a received packet which includes Step 736: “Decod[ing] at least a header portion of the packet at a physical layer device”. Here, “a header portion of the packet” maps to “a set of data associated with the recovered frame”. One or more tags in the recovered frame; or at least a portion of one or more fields from the recovered frame Fig. 7B in Aldaz desecribes recovering “a header portion of the packet” in step 736 including “a destination medium access control (MAC) address”. Determining, based on the identified set of data, whether to forward the recovered frame to a MAC interface Step 740 in Fig. 2B determines whether to “Deactivate the MAC address parser” in step 741 or “activate a MAC device for performing data processing functions 744”. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Aldaz’s practice of packet filtering into Su’s method for detecting multiple simultaneous signals with different MCSs. As Aldaz explains, this can help “perform[] real-time reassembly” of “VoIP traffic” (Aldaz, 0093). As to Claim 17: Su teaches: Receiving, by the PHY controller and from a first front-end block, an indication of a signal having a first modulation Su describes “determining the structure of the neural network” in Fig. 7 “based on ... the modulation scheme configured to the downlink transmission” (Su, 0190). Here, “determining the structure of the neural network based on ... the modulation scheme” demonstrates that the neural network logic includes “logic to receive, from a first front-end block, an indication of a signal having a first modulation”. Assigning, by the PHY controller and based at least in part on the indication, the first front-end block to a first back-end block configured to receive signals having the first modulation Su describes “determining the structure of the neural network” in Fig. 7 “based on ... the modulation scheme configured to the downlink transmission” (Su, 0190). Here, “determining the structure of the neural network based on ... modulation scheme” demonstrates that there is “logic to assign, based at least in part on the indication, the first front-end block to a first back-end block configured to receive signals having the first modulation”. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Patil et al. (US 2018/0110046 A1) describes adjusting the reception window for a beacon to prevent it from colliding with beacons from another access point. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Benjamin Peter Welte whose telephone number is (703)756-5965. The examiner can normally be reached Monday - Friday, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chirag G Shah can be reached at (571) 272-3144. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BENJAMIN PETER WELTE Examiner Art Unit 2477 /GREGORY B SEFCHECK/Primary Examiner, Art Unit 2477
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Prosecution Timeline

Oct 31, 2024
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
64%
Grant Probability
78%
With Interview (+14.7%)
3y 2m (~1y 3m remaining)
Median Time to Grant
Low
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