DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1, 5-6, 8-10, 12-13 and 17-18 have been amended.
Objections to the Claims
Amendments made to claim(s) 8 and 18 have overcome the previous objections. Claim(s) 8 and 18 are no longer objected.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 09/04/2026 with respect to Claim(s) 1-18 have been fully considered but they are not persuasive.
Applicant's arguments with respect to Claim(s) 1-18 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-18 herein.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 recites terms "an isolation layer", “a plurality of elastic conductive pillars” in repetition of parent claims’ 9 and 11 recited same terms. Examiner suggests using appropriate antecedent article for the terms to restore clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Khandros et al. (US 5900738; hereinafter Khandros) in view of Ho et al. (US 20080171453).
Regarding claim 1, Khandros teaches in figure(s) 1-38 An IC testing apparatus, comprising:
a printed circuit board (pc board 442; fig. 27) including a test circuit (semiconductor device 452; col. 4 lines 25-30 :- a production, test or burn-in socket for a semiconductor package or semiconductor device; col. 21 lines 61-62 :- semiconductor package assembly 536 on a mother circuit board; fig. 34);
a plurality of conductive pads (pads 443,444) located on an upper surface of the printed circuit board (442) and electrically connected to the test circuit (452); and
a plurality of elastic conductive pillars (resilient contacts 446) directly integrated onto the conductive pads of the printed circuit board (col. 18 lines 1-10, col. 22 lines 10-15 - Contact structures 446 are mounted on the pads 443 and are comprised of a skeleton 447 and shell 448 construction in the manner shown to provide a resilient contact structure… integrated resilient contacts).
Khandros does not teach explicitly each of the elastic conductive pillars comprising an elastic conductive colloid and a plurality of conductive particles embedded within the elastic conductive colloid.
However, Ho teaches in figure(s) 1-10 each of the elastic conductive pillars (121 in fig. 5c; 32 in fig. 7) comprising an elastic conductive colloid (7) and a plurality of conductive particles (7, 322, 321) embedded within the elastic conductive colloid (para. 37 - deformation of the thin metal layer 322 causes the deformation of the liquid electric conductor 321).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khandros by having each of the elastic conductive pillars comprising an elastic conductive colloid and a plurality of conductive particles embedded within the elastic conductive colloid as taught by Ho in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "a liquid metal with low impedance to obviously reduce the impedance of the conductive element, and it plates the thin meal layer on the surface of the liquid electric conductor to increase the elasticity of the conductive element. Besides, the structure of the conductive element is simple to manufacture easily." (abstract).
Regarding claim 2, Khandros teaches in figure(s) 1-38 the IC testing apparatus of claim 1, further comprising an isolation layer surrounding the elastic conductive pillars (col. 11 lines 10-15 :- layer 229 is covered with another isolation layer 231 of a nickel alloy which is covered with a gold layer 232; fig. 15).
Regarding claim 3, Khandros teaches in figure(s) 1-38 the IC testing apparatus of claim 2, wherein the distance between the isolation layer (231; fig. 15) and the elastic conductive pillars (236) is greater than 0.
Regarding claim 4, Khandros teaches in figure(s) 1-38 the IC testing apparatus of claim 1, wherein the elastic conductive pillars have a plurality of different cross-sectional shapes (different cross-sections of contact pillars in figs. 1-5).
Regarding claim 5, Khandros teaches in figure(s) 1-38 the IC testing apparatus of claim 2, wherein the material of the isolation layer is selected from the group consisting of polyamide (321,322; col. 12 lines 67; fig. 20), PCB materials, silicone, and ceramics.
Regarding claim 6, Khandros teaches in figure(s) 1-38 the IC testing apparatus of claim 1, the conductive particles are selected from the group consisting of metal powders, metal alloy powders, graphite powders, conductive compounds, and conductive plastics (col. 2 lines 15-20 :- electrically conducting filled compliant elastomeric layer).
Regarding claim 7, Khandros teaches in figure(s) 1-38 the IC testing apparatus of claim 2, wherein the height of the isolation layer (231; fig. 15) is approximately 0.2 to 4 times the height of the elastic conductive pillars (228).
Claim(s) 9-11 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Khandros in view of Wang et al. (US 20210249150).
Regarding claim 9, Khandros teaches in figure(s) 1-38 a method of manufacturing an IC testing apparatus, comprising the steps of:
providing a printed circuit board(pc board 442; fig. 27) including a test circuit (semiconductor device 452; col. 4 lines 25-30 :- a production, test or burn-in socket for a semiconductor package or semiconductor device);
forming a plurality of conductive pads (pads 443,444) electrically connected to the test circuit (452) on an upper surface of the printed circuit board (442); and
forming a plurality of elastic conductive pillars (resilient contacts 446) on the conductive pads (col. 18 lines 1-10, col. 22 lines 10-15 - Contact structures 446 are mounted on the pads 443 and are comprised of a skeleton 447 and shell 448 construction in the manner shown to provide a resilient contact structure… integrated resilient contacts).
Khandros does not teach explicitly wherein forming the plurality of elastic conductive pillars comprises:
forming a plurality of patterned spaces corresponding to a layout of the elastic
conductive pillars;
filling a conductive gel containing conductive particles into the patterned spaces;
and
curing the conductive gel to form the elastic conductive pillars on the conductive
pads.
However, Wang teaches in figure(s) 1-2 wherein forming the plurality of elastic conductive pillars comprises:
forming a plurality of patterned spaces corresponding to a layout of the elastic
conductive pillars (abs. - polymeric matrix can be filled with a high loading of conductive and non-conductive particles);
filling a conductive gel containing conductive particles into the patterned spaces (para. 12 - polymeric matrix can be filled with a high loading of conductive and non-conductive particles);
and
curing the conductive gel to form the elastic conductive pillars (108; fig. 1) on the conductive pads. (116; abs. - curing agent for catalyzing crosslinking of the polymeric matrix, conductive metal particles and nonconductive compressible rubber particles dispersed within the polymeric matrix… A moldable interconnect containing the elastomeric conductive composite is also provided.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khandros by having wherein forming the plurality of elastic conductive pillars comprises: forming a plurality of patterned spaces corresponding to a layout of the elastic conductive pillars; filling a conductive gel containing conductive particles into the patterned spaces; and curing the conductive gel to form the elastic conductive pillars on the conductive pads as taught by Wang in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "improved elastomeric conductive composite for use in a moldable interconnect." (abstract).
Regarding claim 10, Khandros teaches in figure(s) 1-38 the method of claim 9, wherein forming the plurality of patterned spaces comprises: forming a sacrificial layer on the printed circuit board; forming the patterned spaces in the sacrificial layer to expose the conductive pads; wherein the sacrificial layer is removed after curing the conductive gel (col. 9 lines 30-50 :- flexible elongate element 187 … by suitable means such as a wedge bond to a sacrificial metal layer 188 as for example an aluminum layer which is secured to the component 102 by a thick photoresist 189 which serves as a standoff. After that step has been completed, the aluminum layer 188 can be sacrificed by etching it away with a suitable etch such as sodium hydroxide. The flexible elongate element 187 can then be coated in the manner hereinbefore described with a shell 190 formed of a nickel cobalt alloy or other suitable material as hereinbefore described to provide a free standing spring-like contact structure 186; fig. 11).
Regarding claim 11, Khandros teaches in figure(s) 1-38 the method of claim 9, further comprising forming an isolation layer on the printed circuit board, the isolation layer surrounding the elastic conductive pillars (col. 11 lines 10-15 :- layer 229 is covered with another isolation layer 231 of a nickel alloy which is covered with a gold layer 232; fig. 15).
Regarding claim 14, Khandros teaches in figure(s) 1-38 the method of claim 11, wherein the height of the isolation layer (231; fig. 15) is approximately 0.2 to 4 times the height of the elastic conductive pillars (228).
Regarding claim 15, Khandros teaches in figure(s) 1-38 the method of claim11, wherein the distance between the isolation layer (231; fig. 15) and the elastic conductive pillars (236) is greater than 0.
Regarding claim 16, Khandros teaches in figure(s) 1-38 the method of claim 11, wherein the material of the isolation layer is selected from the group consisting of polyamide (321,322; col. 12 lines 67; fig. 20), PCB materials, silicone, and ceramics.
Regarding claim 17, Khandros teaches in figure(s) 1-38 the method of claim 9, wherein the conductive particles contained in the conductive gel are selected from the group consisting of metal powders, metal alloy powders, graphite powders, conductive compounds, and conductive plastics (col. 2 lines 15-20 :- electrically conducting filled compliant elastomeric layer).
Claim(s) 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Khandros in view of Wang, and further in view of Beroz et al. (US 20020031905).
Regarding claim 12, Khandros teaches in figure(s) 1-38 the method of claim 11,
Khandros does not teach explicitly wherein the plurality of patterned spaces are formed in the isolation layer to expose the conductive pads.
However, Beroz teaches in figure(s) 1-14 wherein the plurality of patterned spaces (projections 338 patterns; figs. 7) are formed in the isolation layer (342; figs. 7) to expose the conductive pads (352).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khandros by having wherein the plurality of patterned spaces are formed in the isolation layer to expose the conductive pads as taught by Beroz in order to provide "A conductive material, such as copper, is deposited over the first surface of the removable layer and in each of the vias to form one or more flexible leads including projections which extend downwardly in the vias toward the removable layer" (abs.).
Regarding claim 13, Khandros teaches in figure(s) 1-38 the method of claim 11,
Khandros does not teach explicitly wherein forming the elastic conductive pillars and the isolation layer comprises: forming an isolation layer on a sacrificial layer; forming a plurality of patterned spaces in the isolation layer; filling the conductive gel into the patterned spaces and curing the conductive gel to form a plurality of elastic conductive pillars; removing the sacrificial layer; and attaching the elastic conductive pillars together with the isolation layer to the printed circuit board.
However, Beroz teaches in figure(s) 1-14 wherein the step of forming the isolation layer on the printed circuit board comprises: forming an isolation layer (42; figs. 1) on a sacrificial layer (10); forming a plurality of patterned spaces on the isolation layer; filling conductive gel (para. 18 – encapsulants silicone gels) into the patterned spaces and curing the conductive gel to form a plurality of elastic conductive pillars (flexible leads 32); removing the sacrificial layer; and attaching the elastic conductive pillars together with the isolation layer to the printed circuit board (16).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Khandros by having wherein the step of forming the isolation layer on the printed circuit board comprises: forming an isolation layer on a sacrificial layer; forming a plurality of patterned spaces on the isolation layer; filling conductive gel into the patterned spaces and curing the conductive gel to form a plurality of elastic conductive pillars; removing the sacrificial layer; and attaching the elastic conductive pillars together with the isolation layer to the printed circuit board as taught by Beroz in order to provide "A method of making a connection component includes providing a removable layer having first and second surfaces and forming vias at spaced apart first locations of the removable layer" (abstract).
Allowable Subject Matter
Claim(s) 8 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reason for the indication of allowable subject matter:
Regarding claim(s) 8 and 18, the prior art of record alone or in combination fail to anticipate or make obvious the specific limitations of “at least two of the elastic conductive pillars formed on respective ones of the conductive pads supplying the same electrical potential are laterally connected to each other” in combination with all the other limitations as claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JUDY NGUYEN can be reached on 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/Primary Examiner, Art Unit 2858
