DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112 - Indefinite
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, and 4-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, beginning on line 8, recites:
an electro-optical interface electrically coupled to the memory controller and optically coupled to the optical IO port, the electro-optical interface is configured to:
receive, from the memory controller, a memory data stream comprising data stored on the memory;
encode the memory data stream onto a multiplexed optical signal; and
transmit, at the optical IO port, the multiplexed optical signal encoded with the memory data stream.
It is not clear what particular structure is within the scope of “an electro-optical interface” or how it is “configured” to perform the recited functionality. The Examiner notes that this claim language was originally “electro-optical interface protocol”, and the term “protocol” was deleted. The “electro-optical interface protocol” 270 is illustrated as part of the EO Memory Interface 36 in FIG. 2B, and the structure of the “electro-optical interface protocol” 270 is illustrated in FIGS. 3A and 3C and described beginning at PG Pub [0065].
The Examiner also notes that claim 2 recites additional structure including a link controller, a digital electrical layer, and an analog electro-optical layers. This appears to recite at least some of the “EO interface protocol” illustrated in FIG. 3C. This supports an interpretation that the scope of the “EO Interface” in claim 1 is broader than the structure recited in claim 2, and it is not clear what particular structure is within that scope.
Therefore, the particular structure within the scope of the amended claim is not clear. If Applicant does not want to recite the particular structure for performing the recited functionality, then the Examiner suggests writing the claims in means-plus-function form (e.g., invoke an interpretation under 35 USC 112(f)).
Claim 2 recites:
an analog electro-optical layer electrically coupled to the digital electrical layer and optically coupled to the optical IO port, the analog electro-optical layer configured to:
receive, from the digital electrical layer, the plurality of bitstreams comprising the data stored on the memory;
encode, for each of the plurality of wavelengths, the respective each bitstream onto a respective optical signal having a different the wavelength;-and multiplex the optical signals encoded with the bitstreams into the multiplexed optical signal; and
transmit, at the optical IO port, the multiplexed optical signal encoded with the memory data stream.
It is not clear what particular structure is within the scope of the “analog electro-optical layer” or how it is “configured” to perform the recited functionality/results. The Examiner notes that claim 3, which depends from claim 2, recites particular structure for this term. This supports an interpretation that the scope of the “analog electro-optical layer” in claim 2 is broader than the structure recited in claim 3, and it is not clear what particular structure is within that scope.
For the reasons discussed above, claim 3 is not rejected under 35 USC 112(b).
Claim 13, beginning at line 14, recites:
an electro-optical memory interface connecting the memory to the optical IO port of the memory module, the electro-optical memory interface configured to:
generate a memory data stream comprising data stored on the memory;
encode the memory data stream onto the multiplexed input output signal received at the respective optical IO port in the first set; and
transmit, at the optical IO port of the memory module, the multiplexed input optical signal encoded with the memory data stream
It is not clear what particular structure is within the scope of “an electro-optical memory interface” or how it is “configured” to perform the recited functionality.
The Examiner notes that an “electro-optical memory interface” is illustrated in FIG. 2B as element 36 and including the memory controller 362, memory protocol layer 364, EO interface protocol 270, and IO ports 52, 54, 56. However, this claim is not limited to that (or any) particular structure and it is not clear what is within the scope of this element.
Claim 14, beginning at line 13, recites:
an electro-optical host interface connecting the host to optical IO port of the compute module, the electro-optical host interface configured to:
receive, at the optical IO port of the compute module, the multiplexed output optical signal transmitted at the respective optical IO port in the second set;
extract, from the multiplexed output optical signal, a memory data stream comprising the data stored on each memory of a subset of the plurality of memory modules; and
transmit, to the host, the memory data stream comprising the data stored on each memory of the subset of memory modules for the compute module
It is not clear what particular structure is within the scope of “an electro-optical host interface” or how it is “configured” to perform the recited functionality.
Claim 15, beginning at line 8, recites:
the electro-optical host interface of each compute module is further configured to:
receive, from the host, a memory request stream comprising requests to access the data stored on each memory of the subset of memory modules for the compute module;
encode the memory request stream onto the multiplexed input optical signal received at the respective optical IO port in the second set; and
transmit, at the optical IO port of the compute module, the multiplexed input optical signal encoded with the memory request stream.
It is not clear what particular structure is within the scope of “an electro-optical host interface” or how it is “further configured” to perform the recited functionality.
Claim 16, beginning at line 7, recites:
the electro-optical memory interface of each memory module is further configured to:
receive, at the optical IO port of the memory module, the multiplexed output optical signal transmitted at the respective optical IO port in the first set;
extract, from the multiplexed output optical signal, a memory request stream comprising each request to access the data stored on the memory; and
process the memory request stream to generate, responsive to the requests, the memory data stream comprising the data stored on the memory.
It is not clear what particular structure is within the scope of the “electro-optical memory interface” or how it is “further configured” to perform the recited functionality.
Claim 19, beginning at line 3, recites:
the electro-optical interface is further configured to:
receive, at the optical IO port, a multiplexed input optical signal encoded with a memory request stream comprising requests to access the data stored on the memory;
extract the memory request stream from the multiplexed input optical signal; and transmit, to the memory controller, the memory request stream comprising the requests to access the data stored on the memory, and
It is not clear what particular structure is within the scope of the “electro-optical interface” or how it is “further configured” to perform the recited functionality.
Claim 20, beginning at line 3, recites:
the electro-optical interface is further configured to:
encode the memory data stream onto the plurality of multiplexed optical signals; and
transmit, at each of the plurality of optical IO ports, a corresponding one of the plurality of multiplexed optical signals encoded with the memory data stream.
It is not clear what particular structure is within the scope of the “electro-optical interface” or how it is “further configured” to perform the recited functionality.
Claims 2-12 and 14-20 are also rejected because they depend from one or more of the claims rejected above and they fail to further limit the scope in a manner to overcome the rejection.
The claims are rejected above under 35 USC 112(b). However, in the interests of compact prosecution, the claims are also rejected under 35 USC 112(a), Scope of Enablement. In particular, if the claims are interpreted to be merely broadly but not indefinite, then the claims will have a scope that does not appear to be commensurate with the teachings in the application.
Claim Rejections - 35 USC § 112 – Scope of Enablement
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, and 4-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for a limited scope based on the teachings in the application, does not reasonably provide enablement for the full scope recited in the claims. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the invention commensurate in scope with these claims.
MPEP 2164.08 states: “The Federal Circuit has repeatedly held that ‘the specification must teach those skilled in the art how to make and use the full scope of the claimed invention without ‘undue experimentation’.” In re Wright, 999 F.2d 1557, 1561, 27 USPQ2d 1510, 1513 (Fed. Cir. 1993).
Scope of the Claims and Teachings of the Application.
Claim 1, beginning on line 8, recites:
an electro-optical interface electrically coupled to the memory controller and optically coupled to the optical IO port, the electro-optical interface is configured to:
receive, from the memory controller, a memory data stream comprising data stored on the memory;
encode the memory data stream onto a multiplexed optical signal; and
transmit, at the optical IO port, the multiplexed optical signal encoded with the memory data stream.
The term “electro-optical interface” with “configured to” to perform the recited functionality is broad and includes just about every possible EO interface (e.g., a PD or LED) that can be configured, in any way, to perform the recited functionality. In contrast, the present application at FIG. 2B illustrates an “electro-optical interface protocol” 270, which appears to be the structure that performs the recited functionality.
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The structure of the “electro-optical interface protocol” 270 is illustrated in alternative embodiments in FIGS. 3A and 3C.
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The EO Phy Analog 274A in the “electro-optical interface protocol” 270 is illustrated in FIG. 3B.
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This is described beginning at PG Pub [0065]. In other words, the application teaches particular structure, arranged in a particular manner, to achieve the desired results. The application does not appear to teach how to make and use the full scope of the claim.
Claim 2 recites:
an analog electro-optical layer electrically coupled to the digital electrical layer and optically coupled to the optical IO port, the analog electro-optical layer configured to:
receive, from the digital electrical layer, the plurality of bitstreams comprising the data stored on the memory;
encode, for each of the plurality of wavelengths, the respective each bitstream onto a respective optical signal having a different the wavelength;-and multiplex the optical signals encoded with the bitstreams into the multiplexed optical signal; and
transmit, at the optical IO port, the multiplexed optical signal encoded with the memory data stream.
The term “analog EO layer” with “configured to” to perform the recited functionality is broad and includes just about every possible analog EO layer structure that can be configured, in any way, to perform the recited functionality. In contrast, the present application at FIG. 3B (reproduced above) illustrates what appears to be the analog electro-optical layer. In other words, the application teaches particular structure, arranged in a particular manner, to achieve the desired results. The application does not appear to teach how to make and use the full scope of the claim.
Claim 13, beginning at line 14, recites:
an electro-optical memory interface connecting the memory to the optical IO port of the memory module, the electro-optical memory interface configured to:
generate a memory data stream comprising data stored on the memory;
encode the memory data stream onto the multiplexed input output signal received at the respective optical IO port in the first set; and
transmit, at the optical IO port of the memory module, the multiplexed input optical signal encoded with the memory data stream
The term “EO memory interface” with “configured to” to perform the recited functionality is broad and includes just about every possible EO memory interface structure that can be configured, in any way, to perform the recited functionality. In contrast, the present application at FIG. 2B (reproduced above) illustrates that the EO memory interface includes several particular components/structures. In other words, the application teaches particular structure, arranged in a particular manner, to achieve the desired results. The application does not appear to teach how to make and use the full scope of the claim.
Claim 14, beginning at line 13, recites:
an electro-optical host interface connecting the host to optical IO port of the compute module, the electro-optical host interface configured to:
receive, at the optical IO port of the compute module, the multiplexed output optical signal transmitted at the respective optical IO port in the second set;
extract, from the multiplexed output optical signal, a memory data stream comprising the data stored on each memory of a subset of the plurality of memory modules; and
transmit, to the host, the memory data stream comprising the data stored on each memory of the subset of memory modules for the compute module
The term “EO host interface” with “configured to” to perform the recited functionality is broad and includes just about every possible EO host interface structure that can be configured, in any way, to perform the recited functionality. In contrast, the present application at FIG. 2A illustrates that the EO host interface includes several particular components/structures.
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In other words, the application teaches particular structure, arranged in a particular manner, to achieve the desired results. The application does not appear to teach how to make and use the full scope of the claim.
Claim 15, beginning at line 8, recites:
the electro-optical host interface of each compute module is further configured to:
receive, from the host, a memory request stream comprising requests to access the data stored on each memory of the subset of memory modules for the compute module;
encode the memory request stream onto the multiplexed input optical signal received at the respective optical IO port in the second set; and
transmit, at the optical IO port of the compute module, the multiplexed input optical signal encoded with the memory request stream.
This claim recites additional functionality for the EO host interface, but does not recite particular structure consistent with the teachings for achieving the functionality. See the present application at FIG. 2A which illustrates that the EO host interface includes several particular components/structures.
Claim 16, beginning at line 7, recites:
the electro-optical memory interface of each memory module is further configured to:
receive, at the optical IO port of the memory module, the multiplexed output optical signal transmitted at the respective optical IO port in the first set;
extract, from the multiplexed output optical signal, a memory request stream comprising each request to access the data stored on the memory; and
process the memory request stream to generate, responsive to the requests, the memory data stream comprising the data stored on the memory.
This claim recites additional functionality for the EO memory interface, but does not recite particular structure consistent with the teachings for achieving the functionality. See the present application at FIG. 2B which illustrates that the EO memory interface includes several particular components/structures.
Claim 19, beginning at line 3, recites:
the electro-optical interface is further configured to:
receive, at the optical IO port, a multiplexed input optical signal encoded with a memory request stream comprising requests to access the data stored on the memory;
extract the memory request stream from the multiplexed input optical signal; and transmit, to the memory controller, the memory request stream comprising the requests to access the data stored on the memory, and
This claim recites additional functionality for the EO interface, but does not recite particular structure consistent with the teachings for achieving the functionality. See the above discussion of the EO interface.
Claim 20, beginning at line 3, recites:
the electro-optical interface is further configured to:
encode the memory data stream onto the plurality of multiplexed optical signals; and
transmit, at each of the plurality of optical IO ports, a corresponding one of the plurality of multiplexed optical signals encoded with the memory data stream.
This claim recites additional functionality for the EO interface, but does not recite particular structure consistent with the teachings for achieving the functionality. See the above discussion of the EO interface.
In other words, the application teaches how to make and use the inventions using particular structure, materials, and/or steps to implement the functionality and achieve the results. The claims discussed above recite broad, general structure to recite the desired results/functionality without the particular structure taught in the application for achieving the desired results/functionality. The application does not appear to support the broad scope of the claims.
Remaining Claims.
The dependent claims, except for claim 3, add additional limitations but fail to address the issues raised with regard to the independent claims. As a result, the dependent claims also have a scope that would include steps that go beyond the teachings of the present application.
The Claims do not Recite the Particular Structure, Materials, or Steps.
As discussed above, the application teaches how to make and use the invention using particular structure, materials, and steps to implement the recited functionality/results. As also discussed above, the claims recite the desired functionality/results, but do not recite the particular structure, materials, or steps that accomplish the claimed functionality/results. This results in claims having a scope that is broader than the teachings of the application.
When considering the teachings of the application and the scope of the claims, as discussed above, see MPEP 2173.05(g), 4th paragraph:
… Further, without reciting the particular structure, materials or steps that accomplish the function or achieve the result, all means or methods of resolving the problem may be encompassed by the claim. Ariad Pharmaceuticals., Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1353, 94 USPQ2d 1161, 1173 (Fed. Cir. 2010) (en banc). Unlimited functional claim limitations that extend to all means or methods of resolving a problem may not be adequately supported by the written description or may not be commensurate in scope with the enabling disclosure, both of which are required by 35 U.S.C. 112(a) and pre-AIA 35 U.S.C. 112, first paragraph. In re Hyatt, 708 F.2d 712, 714, 218 USPQ 195, 197 (Fed. Cir. 1983); Ariad, 598 F.3d at 1340, 94 USPQ2d at 1167. …
This supports a finding that the broad scope of the claims is not commensurate with the teachings in the disclosure.
While the claims do not need to include every detail of the embodiments disclosed in the application, the scope of the claims must be commensurate with the teachings of the application. However, in the present case, the claims recite broad functional language and desired results while the teachings have a more limited scope in which particular structures are used to achieve the desired results.
No Teaching of a General Case for the Full Scope of the Claims.
The Examiner also notes that there is no teaching of an apparatus with the broad scope recited in the claims. If such a general case were contemplated or discovered by the inventors, its disclosure and a description of its operation would be expected as part of the application in order to support broad claims, such as claims 1 and 13. This is particularly true because, as discussed above, the embodiments that are disclosed in the application require fairly complex and particular structures. These structures would be unnecessary if a general case had been known by the inventors, and yet the application does not include a disclosure of a general case. This supports a conclusion that the scope of the claims is not commensurate with the teachings of the application.
Other Considerations.
The nature of the invention is optical transmission and reception apparatuses and methods. The components used in the various embodiments were known to one of ordinary skill. For example, one or ordinary skill would be familiar with components such as PDs, lasers, optical switches, controllers, signal processors, multiplexers, demultiplexers, modulators, and splitters in the context of the invention. Therefore, no teachings of how to make these individual components is required.
The application teaches how to arrange these elements with other elements in particular combinations in order to achieve the desired results (e.g., see the figures discussed above). These combinations are particular and complex. Nonetheless, one or ordinary skill would know how to make and use the disclosed embodiments of the invention from the teachings of the application.
Furthermore, it would have been obvious that some elements may be modified or replaced with other elements known to have the same or similar functionality, and to make some modifications to the particular structures disclosed.
Similarly, one of ordinary skill would also know how to perform other tasks in the present technological area and related to the invention, such as providing power to components (although power supplies and power specifications are not explicitly taught in the application), and splicing/coupling the electrical and optical components together (although this is not explicitly taught in the application), and managing the temperature of electrical and optical components which are susceptible to performance degradation and undesirable operational variations based on temperature (although this is not explicitly taught in the application), and shielding components from EM interference that can be generated by such devices (although this is not explicitly taught). Although this is not an exhaustive list, the obvious modifications based on the disclosure and the knowledge of one or ordinary skill are nonetheless of a limited scope.
However, these modifications do not address the issues raised above regarding the disparity between the scope of the claims and the teachings of the application.
Experimentation.
As discussed above, the claims have a scope that includes many possible structures, and the application does not teach the full scope of the claims. As a result, if one of ordinary skill were to attempt to make and use the full scope of the claims, it would require making, testing, or otherwise evaluating all (or at least a very large number of) possible combination of structures within the scope of the claims to find what works to perform the claimed functionality. This results in a practically unlimited number of embodiments that would need to be made, tested, or otherwise evaluated to determine which embodiments within the scope of the claims are operative and which are inoperative. In other words, it would require almost infinite experimentation in order to make and use the full scope of the claims.
This supports a finding that undue experimentation would be required to make and use the full scope of the claims.
Conclusion.
After careful consideration the Examiner has concluded that the specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the invention commensurate in scope with these claims. In other words, the specification fails to teach those skilled in the art how to make and use the full scope of the claimed invention without ‘undue experimentation’.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. The prior art of record teaches the general subject matter of the claims, but it does not appear to teach the particular embodiment recited in claim 3. See the discussion of art below.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2011/0231618 (Baker) is the closest art of record. Baker at FIG. 2 illustrates memory modules 113 including memory 112 (see [0016]), optical IO ports at demux 209, OE conversion at optical tx/rx 211, 213 (see [0022]), and a memory controller 104.
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The memory controller 104 is electrically coupled to the tr/rx 201 and transmitters 203, which are optically coupled to the memory 112 via the optical link 108a and the tx/rx 211, 213, which are electrically coupled to the memory 112. See also:
[0016] FIG. 2 shows a first exemplary embodiment of the invention in which a single common optical link 108a transmits a plurality of data streams between a memory controller 104 and memory modules 113 using paired optical transmitters and receivers on opposite sides of link 108a pre-set to communicate at a respective wavelength. FIG. 2 shows the use of separate data (DQ), command (CMD), address (ADD), and clock (CLK) paths between controller 104 and each memory module 113 as is typical in a computer bus structure. It is also possible to send control and address data over the same data paths as is also well known in the art. For brevity, only the data (DQ) optical path will be discussed in detail, it being understood that the optical paths for other data and clock information sent by the controller will be handled the same except for the direction of data/clock pulse flow. It should also be understood that while the data (DQ) paths are bidirectional, the command/address and clock paths are unidirectional in that the dataflow is from controller 104 to the modules 113 and associated memory devices 112.
[0021] Each module 113 also contains a wave division multiplexer/demultiplexer 209 which receives the optically multiplexed signals on optical link 108a and wavelength demultiplexes them in a demutiplexer portion and passes the demuliplexed signals to respective transmitter/receivers 211, which electrically connect to the data (DQ) paths of the memory devices 112. In addition, the demultiplexed optical signals for the command (CMD), address (ADD) (or combined command/address) and clock (CLK) signal paths are passed on to receivers 213 which convert optical signals to electrical signals which are electrically coupled to the electrical command (CMD), address (ADD) and clock (CLK) signal paths of the memory devices 112.
[0022] Data read from memory devices 112 is transmitted on the data (DQ) paths of the memory devices 112 to respective transmitter/receivers 211 where the electrical data is converted to an optical signal at a respective wavelength and sent to multiplexer/demultiplexer 209 where the data on the respective DQ optical paths is combined in the wave division multiplexer of multiplexer/demultiplexer 209. This data is then sent over optical link 108a to multiplexer/demultiplexer 207 where it is demultiplexed and passed to respective transmitter/receivers 201 where the DQ optical data is connected to electrical DQ data which is sent to respective DQ data paths of controller 104. FIG. 2 illustrates the optical coupling of two memory modules 113 to memory controller 104 through the electro-optical converter 205 provided at the memory controller 104 side of optical link 108 and an electro-optical converter and 219 provided on the memory modules 113; however, it should be understood that any number of memory modules 113, containing any number of memory devices 112, may be optically coupled to controller 104 over optical link 108a.
See also FIG. 1 which illustrates a higher-level view showing the memory controller 104, optical link 108, and memory 112, 113.
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See also:
[0014] The present invention uses one or more optical links between a processor and/or a memory controller and a DRAM memory device. The optical link includes, but is not limited, to optical fiber and optical waveguide links as described below in connection with various exemplary embodiments of the invention. FIG. 1 shows a high level block diagram of the present invention. A processor 100 is connected to a memory controller 104 which in turn is connected to a memory module 113 containing one or more memory devices 112 using one or more optical links 108. The memory controller 104 and modules 113 have optical couplers which enable them to connect to the optical links 108 to maintain optical continuity. The modules 113 have optical plug-in connectors to the optical links 108, but also have standard (non-optical) Dual Inline Memory Module (DIMM) connectors 109 for supplying power and other low-frequency signals.
This also shows the memory controller 104 connected to the memory 112, 113 via the optical link 108.
US 2021/0359766 (Sysak) at FIG. 1A illustrates an optical system including a substrate on which electrical and optical ICs are mounted.
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See:
[0051] FIG. 1A shows an example block-level architecture of a system 100 implementing a TeraPHY chiplet 101, in accordance with some embodiments. The system 100 shows a general representation of a multi-chip package (MCP) that is implemented to include the TeraPHY chiplet 101. The system 100 includes the TeraPHY chiplet 101 attached to a substrate 103. The TeraPHY chiplet 101 includes an optical interface that is optically connected to an optical link 105 through which bi-directional optical data communication is performed with another electro-optic device, such as with another TeraPHY chiplet. The system 100 also includes one or more integrated circuit chips 107 (semiconductor chips) attached to the substrate 103. In various embodiments, the one or more integrated circuit chips 107 includes one or more of a central processing unit (CPU), a graphics processing unit (GPU), a visual processing unit (VPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a memory chip, an HBM stack, an SoC, a microprocessor, a microcontroller, a digital signal processor (DSP), an accelerator chip, and/or essentially any other type of semiconductor chip. In various embodiments, the substrate 103 is an organic package and/or interposer. In some embodiments, the substrate 103 includes electrical connections/routings 109 between the TeraPHY chiplet 101 and the one or more integrated circuit chips 107. In some embodiments, the electrical connections/routings 109 are formed within a redistribution layer (RDL) structure formed within the substrate 103. In various embodiments, the RDL structure is implemented in accordance with essentially any RDL structure topology and technology available within the semiconductor packaging industry. Some of the electrical connections/routings 109 within the substrate 103 are configured and used to provide electrical power and reference ground potential to the TeraPHY chiplet 101 and to each of the one or more semiconductor chips 107. Also, some electrical connections/routings 109 within the substrate 103 are configured and used to transmit electrical signals that provide for bi-directional digital data communication between the TeraPHY chiplet 101 and the one or more semiconductor chips 107. In various embodiments, digital data communication through the electrical connections/routings 109 between the TeraPHY chiplet 101 and the one or more semiconductor chips 107 is implemented in accordance with a digital data interconnect standard, such as the Peripheral Component Interconnect Express (PCIe) standard, the Compute Express Link (CXL) standard, the Gen-Z standard, the Open Coherent Accelerator Processor Interface (OpenCAPI), and/or the Open Memory Interface (OMI), among essentially any other digital data interconnect standard.
[0052] The system 100 also includes an optical power supply 111 optically connected to supply continuous wave laser light of one or more controlled wavelengths to the TeraPHY chiplet 101. In some embodiments, the optical power supply 111 is a SuperNova multi-wavelength, multi-port light supply provided by Ayar Labs, Inc. The optical power supply 111 supplies continuous wave (CW) light that optically powers the TeraPHY chiplet 101. In some embodiments, the optical power supply 111 is configured as a photonic integrated circuit (PIC) that generates multiple wavelengths of the CW light, multiplexes the multiple wavelengths of CW light onto a common optical fiber or optical waveguide, and splits and amplifies the multiplexed optical power to multiple output ports of the optical power supply 111 for transmission to multiple corresponding CW light input ports of the TeraPHY chiplet 101.
[0062] The TeraPHY chiplet 101 also includes management circuits 301 and general purpose input/output (GPIO) components 303 for communicating electrical data signals to and from the TeraPHY chiplet 101. In various embodiments, the GPIO components 303 include Serial Peripheral Interface (SPI) components and/or another type of component to enable off-chip data communication. Also, in some embodiments, the TeraPHY chiplet 101 includes many other circuits, such as memory (e.g., SRAM), a CPU, analog circuits, and/or any other circuit that is implementable in CMOS. In some embodiments, the TeraPHY optical I/O chiplet 101 has a coarse wavelength division multiplexing 4-lane (CWDM4) configuration in which each of the optical macros 205-1 to 205-N includes four serializer/deserializer (SerDes) slices (FR-4) or eight SerDes slices (FR-8). In some embodiments, the optical macros 205-1 to 205-N are divided into wavelength transmit (Tx)/receive (Rx) slices, with each Tx/Rx slice including fully integrated analog Tx/Rx front-ends, serialization/deserialization, clock-data-recovery, and microring resonator thermal tuning digital control. In some embodiments, the photonic components integrated in each Tx/Rx slice/optical macro 205-x optical port are based on microring resonators (such as modulators, filters, etc.). In some embodiments, the TeraPHY optical I/O chiplet 101 optically couples to the optical fiber of the fiber array through edge-coupled V-groove structures with embedded mode-converters.
In other words, this teaches that it was known to mount optical and electrical ICs on a common substrate and connected together.
US 2004/0136639 (Kondo) teaches a photonic IC in which optical waveguides 30 are used to interconnect electrical devices 201. See, for example, FIG. 1:
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At either end of the waveguides is a micro-tile element 200 (i.e., an optical transmitter or receiver) for converting between optical and electrical signals. See, for example:
[0078] The micro tile element 200 is a micro tile element having a light emitting or light receiving function. Furthermore, the micro tile element 200 having a light emitting function is paired with the micro tile element 200 having a light receiving function, being provided to each end of a single of the optical wave-guide 30. Namely, the micro tile element 200 having a light emitting function and the micro tile element 200 having a light receiving function are optically connected each other through the optical wave-guide 30.
See FIG. 2 which illustrates a cross-sectional view showing the micro-tile element 200 more clearly.
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It also teaches that a wide variety of materials can be used for the substrate. See [0077]:
[0077] LSIs 201a, 201b and 201c including a plurality of integrated circuits are mounted onto a top surface of a substrate 10. The optical wave-guide 30 that includes a plurality of optical wave-guides and a micro tile element 200 that includes a plurality of micro tile elements are also formed on the top surface of the substrate 10. Any materials, such as glass epoxy, ceramic, glass, plastic, semiconductor, and silicon can be used for the substrate 10. Each of the LSIs 201a, 201b and 201c includes a semiconductor chip, and is flip-chip mounted onto the top surface of the substrate 10 as shown in FIG. 2. Each of the LSIs 201a, 201b and 201c may be mounted onto the substrate 10 by a method other than flip-chip mounting.
US 8,355,605 (Wach) at FIG. 1B illustrates waveguides 150 on a substrate 125.
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Wach also teaches that the waveguides can be single mode or multi-mode. For example, see the paragraph spanning cols 1-2:
The present invention can support disposing two or more optical paths near one another while isolating the light paths to avoid optical crosstalk or unwanted coupling of light between or among the paths. Such optical paths can provide one or more buses for carrying optical communication signals, coherent light, optical power, and/or laser energy; one or more pairs of digital or analog communication links; multiple optical amplifiers; an array of modulated or unmodulated lasers; an array of silicon photonic devices, optical pumping devices, or pump lasers; an optical backplane; two or more optical interconnects, "short range optical interconnects," or "ultra short range optical interconnects;" adjacent optoelectronic or electro-optic devices; two or more waveguides delivering photonic energy including visual illumination for lighting; a compact group of single mode (or multimode) waveguides; an optical network connecting cores for a multi-core processor or components of a central processing/processor unit ("CPU"), a general processing unit ("GPU") or other computing system; a photonic bus for a microprocessor, microcontroller, or multi-chip module ("MCM"); adjacent optical traces or lines on a photonic integrated circuit (" PIC") or a planar lightguide circuit ("PLC"), also known as a planar lightwave circuit; waveguides attached to, integrated with, or embedded in a substrate; or some other appropriate device, application, or system involving light transmission, for example (not an exhaustive list).
And see the paragraph spanning cols 5-6:
The optical signal 575 propagates on the optical waveguide 150B as one or more waves of oscillating electrical and magnet fields, as electromagnetic radiation, and/or as photons. The optical waveguide 150B (as well as the optical waveguide 150A) is typically single mode (or mono-mode), but may alternatively be bimodal or multimodal. As an alternative to an optical signal 575 that is modulated to convey digital or analog information, the optical waveguide 150B can transmit un-modulated light. Such un-modulated light can power a electrical device that converts the light into electricity, provide photonic energy for pumping an optically pumped laser or an optical amplifier, stimulate photonic emissions of a material, generate illumination, etc.
See col 7, the para beginning at line 43 regarding the waveguide being formed on a chip or die as a PLC or PIC:
The exemplary system 100 comprises a substrate 125 with a face or top surface 130. The optical waveguides 150 can be buried into or under the surface 130 or attached thereto. The system 100 exemplifies a PLC or PIC that comprises optical, electrical, and optoelectronic features or components. An array of lasers 160 couples light into the optical waveguides 150, while an array of detectors 165 receives the light. In an exemplary embodiment, the array of lasers 160 are pump lasers that energize the optical waveguides 150 as a silicon photonic circuit. In certain exemplary embodiments, each optical waveguide 150 comprises a lasing cavity. Thus, light can circulate or resonant in each optical waveguide 150.
See also col 9, the para beginning at line 13:
In certain exemplary embodiments, the waveguides 150 (and other elements illustrated in FIG. 1B and/or other waveguide embodiments disclosed herein) can be mounted on the substrate 125. The substrate 125 can comprise a plate, block, sheet, wafer, or slab of material, with a composition of glass, silica, sapphire, aluminum oxide, ceramic, or silicon, for example. In certain embodiments, the substrate 125 is an optical bench or a silicon optical bench ("SiOB"). In certain exemplary embodiments, the waveguides 150 are integrated in or grown on a semiconductor material, such as a silicon-based material, a crystalline material, a single crystal, InGaAs, germanium, InP, III-V material, III-V semiconductor material, etc. (along with other optical, electrical, and/or optoelectronic elements). Such components can be either monolithically integrated or hybrid integrated, for example. The waveguides 150 and associated devices can be grown on, embedded in, or bonded to a common substrate (for example the substrate 130). The substrate 130 can provide a foundation comprising (or substantially consisting of) silicon with attached optical waveguides, for example as a crystal or as a monolithic platform. Further the waveguides 150 can have a format of "silicon-on-insulator," "silica-on-silicon," or "ribbed waveguide." Accordingly, the optical, optoelectronic, and/or electronic components of the system 100 can be a unitary structure, a monolithic system or "chip," or a collection of elements fastened or bonded together. Further, the system 100 can be implemented on a silicon, lithium niobate, or indium phosphide substrate, either as a monolithic or hybrid device.
US 2010/0008675 (De Dobbelaere) at FIG. 3 illustrates an integrated optical transceiver including a PD 106 and a laser 104.
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FIG. 3 illustrates another view showing the substrate 130, transmitter 124, receiver 126, optical fiber 144, and ferrule 140.
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FIGS. 5A and 5B illustrate different views of an embodiment in which the laser 184 and PD are located on a die 182 in a recess 194, and are further located in recess 192.
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See also, for example:
[0062] FIG. 5A shows a front sectional view of one embodiment of a packaged edge-operating integrated transceiver 180. FIG. 5B shows a top view of the packaged transceiver 180. As shown, the packaged transceiver 180 can includes a packaging substrate 190 that defines a first recess 194 dimensioned to allow mounting of a die 182. The example die 182 is shown to have mounted on it an edge-emitting laser-diode 184 and an edge-detecting photo-diode 186. In one embodiment, the die 182, laser-diode 184, and photo-diode 186 assembly can be similar to that described above in reference to FIGS. 4A-4C.
[0063] In one embodiment, as shown in FIG. 5A, the packaging substrate 190 can also define a second recess 192 that allows access to the mounted die 182 (or access to the first recess for mounting the die 182), and/or to provide protection of the die/laser/photo-diode assembly. As described above in reference to FIG. 3, the packaging substrate (130 in FIG. 3) does not necessarily need to have a recess for mounting of the die (122). Thus, it will be understood that any number of die/substrate mounting configurations are possible.
2019/0158183 (Butrie) at FIG. 1A teaches an optical transceiver including lasers 106 and PDs 108 on one substrate 104, and a PLC 116 on another substrate 114.
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Butrie teaches that the PLC can perform a variety of optical signal processing functions. See, for example:
[0029] In some implementations, PLC 116 may receive an optical signal from laser 106 (e.g., via lens 112), process the optical signal, and provide the optical signal to optical fiber 118 for output. Additionally, or alternatively, PLC 116 may receive an optical signal from optical fiber 118, process the optical signal, and provide the optical signal to photodiode 108 (e.g., via lens 112) for photodetection. Additionally, or alternatively, PLC 116 may receive the optical signal from and/or provide the optical signal to another optical device, such as another PLC 116 or the like.
[0030] In some implementations, PLC 116 and/or one or more other optical devices of substrate 114 may perform a particular processing technique on an optical signal, such as optical multiplexing, optical demultiplexing, polarization combining, polarization splitting, polarization rotation, modulation, or the like. For example, PLC 116 may include a 90-degree optical hybrid circuit that combines an optical signal with an oscillation signal. Processing performed by PLC 116 is described in detail, herein, with regard to FIGS. 3A-3C.
See also FIGS. 3A-3C.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARREN WOLF whose telephone number is (571)270-3378. The examiner can normally be reached Monday through Friday, 7:00 AM to 3:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KENNETH N. VANDERPUYE can be reached at 571-272-3078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DARREN E WOLF/Primary Examiner, Art Unit 2634
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