DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the 35 U.S.C. 103 rejections for claims 9-10 and 15-19 have been considered and are persuasive. Accordingly, these rejections have been withdrawn.
Applicant’s arguments with respect to the 35 U.S.C. 103 rejections for claims 1-4 have been considered but are not persuasive.
In response to applicant's argument that the references fail to show certain features of the applicant’s invention as recited in claim 1, specifically, a “a control circuit configured to generate a start signal corresponding to the coding block; wherein in a video encoding mode, the control circuit further generates an indication signal indicating whether an image block of the coding block exists, and the mode decision circuit processes the image block according to the indication signal” it is noted that this limitation is interpreted according to the broadest reasonable interpretation as would be understood by one of ordinary skill in the art such that the reference Tsuji teaches all recited features of the limitation. Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 cite, “[0016] NPL 3 discloses a decision method for the split_cu_flag syntax value, the pred_mode_flag syntax value, the part_mode syntax value, the split_tu_flag syntax value, the intra prediction direction, the motion vector, and the like to minimize a coding cost J based on the Lagrange multiplier λ.
[0017] Referring to 4.8.3 Intra/Inter/PCM mode decision in NPL 3, a decision process for the split_cu_flag syntax value, the pred_mode_flag syntax value, and the part_mode syntax value will be described in brief below.
[0018] In this section, a CU mode decision process for determining the pred_mode_flag syntax value and the part_mode syntax value for a CU is disclosed. A process for a CU partitioning shape for determining the split_cu_flag syntax value by recursively executing the CU mode decision process is also disclosed.
[0074] The entropy encoder 1056 entropy-encodes the split_cu_flag syntax value, the pred_mode_flag syntax value, the part_mode syntax value, the split_tu_flag syntax value, the difference information of the intra prediction direction, and the difference information of the motion vector determined by the estimator 1055, and the transform quantization value.
[0167] In the embodiment, since the prediction mode selector 1044 evaluates predetermined prediction modes in addition to the prediction mode transcoded by the H.264 prediction mode transcoder 1041 to select a prediction mode used by the second video encoder 105 based on the evaluation results, the possibility that the second video encoder 105 can use a prediction mode higher in coding efficiency than the prediction modes transcoded by the H.264 prediction mode transcoder 1041 is increased. In other words, the coding efficiency can be improved.
[0168] In the first embodiment, the additional prediction mode generator 1042 generates Planar prediction as a temporary additional H.265 prediction mode. In the second embodiment, the additional prediction mode generator 1042 generates temporary additional H.265 prediction modes as temporary additional H.265 prediction modes using the concept of MPM (Most Probable Mode) based on the H.265/HEVC standard.
[0199] An information processing system shown in FIG. 8 includes a processor 1001, a program memory 1002, a storage medium 1003 for storing video data, and a storage medium 1004 for storing a bitstream. The storage medium 1003 and the storage medium 1004 may be different storage media, or may be storage areas on the same storage medium. As the storage medium, a magnetic storage medium such as a hard disk can be used.” While applicant is correct in noting that out of the various flags listed in Tsuji, none are explicitly labeled to be an indication signal about whether a coding block exists, examiner notes that under a broad reasonable interpretation to one of ordinary skill in the art, these flags can be interpreted to indicate that a block being processed exists by virtue of being applicable flags to a block that must obviously exist. Therefore, they may be interpreted as indication flags. Further, while applicant is also correct in noting that there does not appear to be a signal named in Tsuji as an explicit “start” signal, examiner notes that under a broad reasonable interpretation to one of ordinary skill in the art, there will be a signal of some kind that causes the processor to start, otherwise the process will not take place. Tsuji teaches the process taking place. Without having to be named explicitly, the preliminary signal that causes the process to take place is understood to exist as a start signal in a manner that teaches the limitation broadly, and is therefore taught by Tsuji. Therefore, Tsuji teaches “a control circuit configured to generate a start signal corresponding to the coding block; wherein in a video encoding mode, the control circuit further generates an indication signal indicating whether an image block of the coding block exists, and the mode decision circuit processes the image block according to the indication signal.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically taught as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Segall et al. (US 20120236936) (hereinafter Segall) in view of Tsuji et al. (US 20160337652) (hereinafter Tsuji).
Regarding claim 1, Segall teaches wherein the input data comprises a coding block (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall),
However, Segall does not explicitly teach the hardware and signaling as needed for the limitations of claim 1.
Tsuji, in a similar field of endeavor, teaches A video encoder coupled to an external memory and configured to encode an input data to generate an output data,
the video encoder comprising: a control circuit configured to generate a start signal corresponding to the coding block; a data loading circuit coupled to the control circuit and configured to read the coding block from the external memory according to the start signal; a mode decision circuit coupled to the control circuit and configured to process the coding block according to the start signal and generate an intermediate data; and an entropy coding circuit coupled to the mode decision circuit and configured to generate the output data according to the intermediate data; wherein in a video encoding mode, the control circuit further generates an indication signal indicating whether an image block of the coding block exists, and the mode decision circuit processes the image block according to the indication signal (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to modify the teaching of Segall to include the teaching of Tsuji so that in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode.
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Regarding claim 2, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 1, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the coding block is located at a right boundary of a frame (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 3, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 1, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the coding block is N by N pixels in size, the image block is N/2 by N/2 pixels or N/4 by N/4 pixels in size, and N is four or an integer multiple of four (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 4, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 3, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein N is 32 (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall), and
the video encoding mode is High Efficiency Video Coding (H.265) or Alliance for Open Media (AOMedia) Video 1 (AV1) (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode).
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Allowable Subject Matter
Claim(s) 5-8 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim(s) 9-20 is/are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 5 contains the limitations regarding a video encoder that uses a mode decision circuit to process a first image block to generate intermediate data, where the mode decision circuit processes a second image block before processing the first image block, when the indication signal is a preset value, the mode decision circuit outputs a second block coding method of the second image block to be used as a first block coding method of the first image block. At the time of the effective filing date of the application, these limitations had not been fully anticipated and it would not have been obvious to one of ordinary skill in the art to combine elements of the prior art to meet this limitation. The claim(s) depending on these claim(s) contain allowable subject matter for the reasons concerning these claim(s).
The following is an examiner’s statement of reasons for allowance: independent claim 9 contains the limitations regarding a video encoder receiving the input of a first and second to be processed block, where start signals are generated for the first and second block so that they may be read and processed by a data loading circuit and mode decision circuit in order, wherein the first to be processed block is adjacent to the second to be processed block, and in a video encoding mode, the control circuit generates the second start signal before the mode decision circuit in particular finishes processing the first to be processed block. At the time of the effective filing date of the application, these limitations had not been fully anticipated and it would not have been obvious to one of ordinary skill in the art to combine elements of the prior art to meet this limitation. Independent claim(s) 16 is/are allowed for the same reasons as claim 9. The dependent claims are allowed for the reasons concerning the independent claim(s).
The closest prior art, Segall et al. (US 20120236936), Tsuji et al. (US 20160337652), Feng (US 20230050596), Cai et al. (US 20170188035), Lee et al. (US 20090103620), Urban et al. (US 20200053368), Chen et al. (US 20240223768), Tu et al. (US 20160261870), Ryder et al. (US 20250016339), Xiu et al. (US 20240259567), Kang et al. (US 20210274176), Ho et al. (US 10091500), Chiu et al. (US 10244248) either singularly or in combination fail to anticipate or render obvious the above described limitations. While the prior art contains teachings regarding the sequential order processing of N/2 blocks, and also parallel processing of blocks, the prior art is silent with regard to a video encoder that uses a mode decision circuit to process a first image block to generate intermediate data, where the mode decision circuit processes a second image block before processing the first image block, when the indication signal is a preset value, the mode decision circuit outputs a second block coding method of the second image block to be used as a first block coding method of the first image block or a video encoder that uses a mode decision circuit to process a first and second block to generate intermediate data that handles first through fourth coding blocks of the first block, all of N/2 size, that are processed sequentially in order, but after the third coding block is processed, a second start signal is generated to signal the processing of the second block before the fourth block is processed. Further, regarding claims 9 and 16, applicant’s 06/11/2026 remarks pages 6-8 cite, “Claim 9 requires that "the first to-be-processed block is adjacent to the second to-be- processed block, and in a video encoding mode, the control circuit generates the second
start signal before the mode decision circuit finishes processing the first to-be-processed
block."
This limitation defines an inter-block pipelining scheme. As disclosed in the present
application (see FIG. 7 and FIG. 8A, step 5816), while the mode decision circuit is still
processing the first to-be-processed block, the control circuit already issues the second start
signal so that the data loading circuit can begin reading the second, adjacent to-be- processed block from external memory. Because external memory access is comparatively
slow, issuing the second start signal early hides the data-loading latency and improves
encoding throughput.
The Examiner has already conceded that Segall does not disclose the required
hardware and signaling, expressly stating that "Segall does not explicitly teach the
hardware and signaling as needed for the limitations of claim 9," and relies on Segall only for the notion that "the second set of blocks may start being decoded before the first set of
blocks are completely decoded," with Tsuji supplied for the circuit architecture. This is
incorrect for the following reasons.
First, Segall's "parallel processing" is intra-macroblock intra-prediction parallelism,
not the inter-block start-signal pipelining of claim 9. Segall divides the sub-blocks within a
single macroblock into two sets (e.g., a checkerboard pattern) so that the second set may
begin being processed before the first set is complete, because their prediction
dependencies permit it. This is parallelism among sub-blocks inside one block. By contrast,
claim 9 concerns two adjacent to-be-processed blocks, where the control circuit issues the start signal for the next adjacent block before finishing the previous one-i.e., inter-block pipelining for data loading. Segall's intra-block scheme neither discloses nor suggests this
inter-block signaling, and characterizing it as such is impermissible hindsight.
Second, Tsuji does not disclose any control-circuit-to-data-loading-circuit signaling,
let alone the early issuance of a second start signal. As noted in connection with claim 1, Tsuji discloses only conventional functional blocks and passive buffers; it has no control circuit that generates a start signal corresponding to a coding block, and therefore cannot
disclose generating a second start signal before the mode decision circuit finishes
processing a first block. Tsuji's references to memory and processing are at the highest
level of generality and supply none of this signaling.” Examiner agrees with applicant’s assertion that the teaching of Segall would not be read onto the limitations of claims 9 and 16 by one of ordinary skill in the art, and further, therefore, the prior art does not teach a video encoder receiving the input of a first and second to be processed block, where start signals are generated for the first and second block so that they may be read and processed by a data loading circuit and mode decision circuit in order, wherein the first to be processed block is adjacent to the second to be processed block, and in a video encoding mode, the control circuit generates the second start signal before the mode decision circuit in particular finishes processing the first to be processed block. Therefore, at the time of the effective filing date of the application, these limitations had not been fully anticipated and it would not have been obvious to one of ordinary skill in the art to combine elements of the prior art to meet this limitation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew D Kim whose telephone number is (571)272-3527. The examiner can normally be reached Monday - Friday: 9:30am - 5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Ustaris can be reached at (571) 272-7383. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW DAVID KIM/Primary Examiner, Art Unit 2483
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