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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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The information disclosure statement(s) (IDS) submitted on 11/01/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically taught as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 9-10, and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Segall et al. (US 20120236936) (hereinafter Segall) in view of Tsuji et al. (US 20160337652) (hereinafter Tsuji).
Regarding claim 1, Segall teaches wherein the input data comprises a coding block (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall),
However, Segall does not explicitly teach the hardware and signaling as needed for the limitations of claim 1.
Tsuji, in a similar field of endeavor, teaches A video encoder coupled to an external memory and configured to encode an input data to generate an output data,
the video encoder comprising: a control circuit configured to generate a start signal corresponding to the coding block; a data loading circuit coupled to the control circuit and configured to read the coding block from the external memory according to the start signal; a mode decision circuit coupled to the control circuit and configured to process the coding block according to the start signal and generate an intermediate data; and an entropy coding circuit coupled to the mode decision circuit and configured to generate the output data according to the intermediate data; wherein in a video encoding mode, the control circuit further generates an indication signal indicating whether an image block of the coding block exists, and the mode decision circuit processes the image block according to the indication signal (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to modify the teaching of Segall to include the teaching of Tsuji so that in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode.
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Regarding claim 2, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 1, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the coding block is located at a right boundary of a frame (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 3, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 1, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the coding block is N by N pixels in size, the image block is N/2 by N/2 pixels or N/4 by N/4 pixels in size, and N is four or an integer multiple of four (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 4, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 3, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein N is 32 (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall), and
the video encoding mode is High Efficiency Video Coding (H.265) or Alliance for Open Media (AOMedia) Video 1 (AV1) (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode).
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Regarding claim 9, Segall teaches wherein the input data comprises a first to-be-processed block and a second to-be-processed block (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall),
wherein the first to-be-processed block is adjacent to the second to-be-processed block, and in a video encoding mode, the control circuit generates the second start signal before the mode decision circuit finishes processing the first to-be-processed block (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
However, Segall does not explicitly teach the hardware and signaling as needed for the limitations of claim 9.
Tsuji, in a similar field of endeavor, teaches A video encoder coupled to an external memory and configured to encode an input data to generate an output data,
the video encoder comprising: a control circuit configured to generate a first start signal corresponding to the first to-be-processed block and a second start signal corresponding to the second to-be-processed block; a data loading circuit coupled to the control circuit and configured to read the first to-be-processed block from the external memory according to the first start signal and read the second to-be-processed block from the external memory according to the second start signal; a mode decision circuit coupled to the control circuit and configured to process the first to-be-processed block according to the first start signal, process the second to-be-processed block according to the second start signal, and generate an intermediate data; and an entropy coding circuit coupled to the mode decision circuit and configured to generate the output data according to the intermediate data (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode);
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to modify the teaching of Segall to include the teaching of Tsuji so that in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode.
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Regarding claim 10, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 9, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the first to-be-processed block is N by N pixels in size, the second to-be-processed block is N by N pixels in size, and N is four or an integer multiple of four (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 15, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 10, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein N is 32, and the video encoding mode is MPEG-4 Part 10 Advanced Video Coding (H.264) (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 16, Segall teaches wherein the input data comprises a first block and a second block, and the first block is adjacent to the second block (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall), the video encoder comprising:
in a second video encoding mode, the control circuit generates the second start signal before the mode decision circuit finishes processing the first block; wherein the first block and the second block are both N by N pixels in size, and N is four or an integer multiple of four (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
However, Segall does not explicitly teach the hardware and signaling as needed for the limitations of claim 16.
Tsuji, in a similar field of endeavor, teaches A video encoder coupled to an external memory and configured to encode an input data to generate an output data,
a control circuit configured to generate a first start signal corresponding to the first block and a second start signal corresponding to the second block; a data loading circuit coupled to the control circuit and configured to read the first block from the external memory according to the first start signal and read the second block from the external memory according to the second start signal; a mode decision circuit coupled to the control circuit and configured to process the first block according to the first start signal, process the second block according to the second start signal, and generate an intermediate data; and an entropy coding circuit coupled to the mode decision circuit and configured to generate the output data according to the intermediate data; wherein in a first video encoding mode, the control circuit generates the second start signal after the mode decision circuit finishes processing the first block (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode and in a first mode, the blocks may be coded sequentially in order);
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to modify the teaching of Segall to include the teaching of Tsuji so that in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode.
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Regarding claim 17, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 16, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the first video encoding mode is High Efficiency Video Coding (H.265) or Alliance for Open Media (AOMedia) Video 1 (AV1) (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode), and
the second video encoding mode is MPEG-4 Part 10 Advanced Video Coding (H.264) (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Regarding claim 18, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 17, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein N is 32 (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall).
Regarding claim 19, the combination of Segall and Tsuji teaches all aforementioned limitations of claim 17, and is analyzed as previously discussed.
Furthermore, the combination of Segall and Tsuji teaches wherein the second block is located at a right boundary of a frame (see Segall paragraphs 26-27, and 40-43 regarding H.264 coding method, NxN sized coding blocks and N/2 or N/4 sized image blocks where N is 32, where input blocks are encoded and in some cases as a second mode, a block that is considered a second block due to being part of a second group may be processed before a block that is considered a first block due to being part of a first group before the first to be processed block is finished processing- it is obvious that if a frame is coded, there will be a first or second coding block located at a right boundary of a frame due to the checkerboard pattern of the grouping of Segall), and
in the first video encoding mode, the control circuit further generates an indication signal indicating whether an image block of the second block exists, and the mode decision circuit processes the image block according to the indication signal (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199 regarding processor control circuit and memory, flag syntax used to indicate various parameters, H.264 and H.265 coding modes and signals and a system of encoding a video with input video data and determining coding modes to generate intermediate data that eventually is entropy coded to generate output data according to intermediate data- one of ordinary skill would recognize that it is obvious that for video data to be input, it would need to be stored on some type of memory to load the data and coding block and that in the starting of the coding, some sort of start signal would be obviously included in order to start coding, and that it is obvious that the presence of split coding unit syntax indicates that image blocks of the coding blocks exist so that the decided mode may be used, and that the prediction mode flag indicates the mode- in combination with Segall, the memory, processor, methods, modes, and signals may be for first or second blocks to encode).
One would be motivated to combine these teachings in order to provide enhanced coding techniques for encoding video (see Tsuji paragraphs, 2, 16-18, 74, 113, 167-168, and 199).
Allowable Subject Matter
Claim(s) 5-8, 11-14, and 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 5 contains the limitations regarding a video encoder that uses a mode decision circuit to process a first image block to generate intermediate data, where the mode decision circuit processes a second image block before processing the first image block, when the indication signal is a preset value, the mode decision circuit outputs a second block coding method of the second image block to be used as a first block coding method of the first image block. Claims 11 and 20 contain the limitations regarding a video encoder that uses a mode decision circuit to process a first and second block to generate intermediate data that handles first through fourth coding blocks of the first block, all of N/2 size, that are processed sequentially in order, but after the third coding block is processed, a second start signal is generated to signal the processing of the second block before the fourth block is processed. At the time of the effective filing date of the application, these limitations had not been fully anticipated and it would not have been obvious to one of ordinary skill in the art to combine elements of the prior art to meet this limitation. The claim(s) depending on these claim(s) contain allowable subject matter for the reasons concerning these claim(s).
The closest prior art, Segall et al. (US 20120236936), Tsuji et al. (US 20160337652), Feng (US 20230050596), Cai et al. (US 20170188035), Lee et al. (US 20090103620), Urban et al. (US 20200053368), Chen et al. (US 20240223768), Tu et al. (US 20160261870), Ryder et al. (US 20250016339), Xiu et al. (US 20240259567), Kang et al. (US 20210274176), Ho et al. (US 10091500), Chiu et al. (US 10244248) either singularly or in combination fail to anticipate or render obvious the above described limitations. While the prior art contains teachings regarding the sequential order processing of N/2 blocks, and also parallel processing of blocks, the prior art is silent with regard to a video encoder that uses a mode decision circuit to process a first image block to generate intermediate data, where the mode decision circuit processes a second image block before processing the first image block, when the indication signal is a preset value, the mode decision circuit outputs a second block coding method of the second image block to be used as a first block coding method of the first image block or a video encoder that uses a mode decision circuit to process a first and second block to generate intermediate data that handles first through fourth coding blocks of the first block, all of N/2 size, that are processed sequentially in order, but after the third coding block is processed, a second start signal is generated to signal the processing of the second block before the fourth block is processed. Therefore, at the time of the effective filing date of the application, these limitations had not been fully anticipated and it would not have been obvious to one of ordinary skill in the art to combine elements of the prior art to meet this limitation.
Conclusion
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/MATTHEW DAVID KIM/Primary Examiner, Art Unit 2483