DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1 (figs. 1-3 & 5A-6C) directed to claims 1-5 & 8-12 in the reply filed on 9/8/2026 is acknowledged. The traversal is on the ground(s) that figures 10 and 11 should be grouped with species 1 as there is only a minor derivation between the structures shown nor does any claim recite a planar shape such that claims 1-5 and 8-12 read on Figs. 10-11 to the extent they read on Figs. 1-3 & 5A-6C. The Examiner conceded that the inclusion of Figs. 10-11 with Species 1 does not currently create a search burden given that claims 1-5 and 8-12 read on all figures 1-3, 5A-6C & 10-11. However as the Applicant has argued that these different shaped pads and opening section (circle and square) are related in a single embodiment the Examiner may consider “change in shape” as an obvious design choice if this feature is claimed in the future.
The requirement is still deemed proper and is therefore made FINAL.
Claims 6-7 and 13-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PG. Pub. 2017/0084556).
Regarding claim 1 – Chen teaches a wiring substrate (fig. 2-2a, 300/300a) having, on a surface, a mounting pad (see mounting pad shown in figure 2a) for mounting a semiconductor device, the wiring substrate (300/300a) comprising: a metal pad (114 [paragraph 0031] Chen states, “redistribution layer (RDL) 114”) provided on one of main surfaces of a base material (see base material below the metal pad 114 shown in figure 2); an insulating layer (108 [paragraph 0031] Chen states, “a dielectric 108, which is designed to isolate the RDL 114 from moisture or reaction”) being provided to cover a side surface of the metal pad (114; see fig. 2a) and at least part of an upper surface of the metal pad (114; see fig. 2a), and being provided with an opening section (see opening of the insulating layer 108) that exposes a part of the upper surface of the metal pad (114); and a metal layer (115 [paragraph 054] Chen states, “bump 115 is a solder bump, solder ball”; solder ball and solder bump will be made of a metal) provided on the metal pad (114) exposed through the opening section (see fig. 2a), wherein a pad area of the mounting pad (114) is defined by the opening section formed in the insulating layer (108), and the wiring substrate (300/300a) further comprises an etching barrier layer (118 [paragraph 0057] Chen states, “the barrier 118 has an etch resistance greater than the RDL 114 and the polymeric material 108”) provided between the upper surface of the metal pad (114) and the insulating layer (108), the etching barrier layer (118) being provided to surround a lower end of the opening section (figure 3B shows the etching barrier layer 118 surrounding the opening section) and extending outward from the lower end (bottom surface of insulating layer 108 at the opening section) of the opening section toward an outer periphery (see outer periphery at element 117).
Regarding claim 2 – Chen teaches the wiring substrate according to claim 1, wherein at least an end of the etching barrier layer (figs. 2-2a, 118) on the opening section side is in contact with the metal layer (115; claimed structure shown in figure 2a).
Regarding claim 3 – Chen teaches the wiring substrate according to claim 1, wherein the etching barrier layer (fig. 2a, 118 [paragraph 0036] Chen states, “the barrier 118 includes titanium (Ti), aluminum (Al) or alloy thereof”) is made of a metal different from a metal of which the metal pad (114 [paragraph 0035] Chen states, “RDL 114 is substantially made with copper (Cu)”) is made (etching barrier layer 118 is made of titanium and metal pad 114 is made of copper).
Regarding claim 4 – Chen teaches the wiring substrate according to claim 1, wherein the etching barrier layer (fig. 2a, 118) is made of an inorganic material ([paragraph 0036] Chen states, “the barrier 118 includes titanium (Ti), aluminum (Al) or alloy thereof”; the metals titanium and aluminum are inorganic materials).
Regarding claim 8 – Chen teaches a manufacturing method of a wiring substrate (fig. 2-2a, 300/300a) having, on a surface, a mounting pad (see mounting pad shown in figure 2a) for mounting a semiconductor device, the manufacturing method includes steps of: forming an etching barrier layer (118 [paragraph 0057] Chen states, “the barrier 118 has an etch resistance greater than the RDL 114 and the polymeric material 108”) on a metal pad (114 [paragraph 0031] Chen states, “redistribution layer (RDL) 114”) provided on one of main surfaces of a base material (see base material below the metal pad 114 shown in figure 2); forming an insulating layer (108 [paragraph 0031] Chen states, “a dielectric 108, which is designed to isolate the RDL 114 from moisture or reaction”) covering a side surface of the metal pad (114; see fig. 2a) and at least part of an upper surface of the metal pad (114; see fig. 2a), and being provided with an opening section (see opening of the insulating layer 108) that exposes a part of the upper surface of the metal pad (114); and forming a metal layer (115 [paragraph 054] Chen states, “bump 115 is a solder bump, solder ball”; solder ball and solder bump will be made of a metal) on the metal pad (114) exposed through the opening section (see fig. 2a), wherein a pad area of the mounting pad (114) is defined by the opening section formed in the insulating layer (108), and the etching barrier layer (118) is formed to surround a lower end of the opening section (figure 3B shows the etching barrier layer 118 surrounding the opening section) and extend outward from the lower end (bottom surface of insulating layer 108 at the opening section) of the opening section toward an outer periphery (see outer periphery at element 117).
Regarding claim 9 – Chen teaches the manufacturing method of the wiring substrate according to claim 8, wherein the metal layer (fig. 2a, 115) is formed to be in contact with at least an end of the etching barrier layer (118) on the opening section side (figure 2a shows the metal layer 115 being in contact with an end of the etching barrier layer 118 at the opening section side).
Regarding claim 10 – Chen teaches the manufacturing method of the wiring substrate according to claim 8, wherein the etching barrier layer (fig. 2a, 118 [paragraph 0036] Chen states, “the barrier 118 includes titanium (Ti), aluminum (Al) or alloy thereof”) is made of a metal different from a metal of which the metal pad (114 [paragraph 0035] Chen states, “RDL 114 is substantially made with copper (Cu)”) is made (etching barrier layer 118 is made of titanium and metal pad 114 is made of copper).
Regarding claim 11 – Chen teaches the manufacturing method of the wiring substrate according to claim 8, wherein the etching barrier layer (fig. 2a, 118) is made of an inorganic material ([paragraph 0036] Chen states, “the barrier 118 includes titanium (Ti), aluminum (Al) or alloy thereof”; the metals titanium and aluminum are inorganic materials).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Parikh et al. (US PG. Pub. 2003/0194872).
Regarding claim 5 – Chen teaches the wiring substrate according to claim 1, wherein an end of the etching barrier layer on the opening section side protrudes toward a center of the opening section, relative to an inner peripheral surface of the opening section.
Parikh teaches wherein an end of the etching barrier layer (fig. 7, 54 [paragraph 0025] Parikh states, “an intermediate layer 54, such as a barrier layer and/or an etch stop, e.g., SiN”) on the opening section side (62/64 [paragraph 0026 & 0033] Parikh states, “vertical interconnect opening 62…undercuts 64”) protrudes toward a center of the opening section (62/64), relative to an inner peripheral surface of the opening section (figure 7 shows the etching barrier layer extending into the opening and overlapping with the opening 62/64).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the wiring substrate having an etching barrier layer that extends to an opening section and is flush with the opening section as taught by Chen with the etching barrier layer protrudes towards a center of the opening section relative to an inner peripheral surface of the opening section as taught by Parikh because Parikh states, “the undercuts created by the processes described herein result in a large surface area between the underlying metal feature and the metal deposited in the interconnects. The large surface area between the underlying metal feature and the metal deposited in the interconnects typically decreases the resistance of the device” [paragraph 0042].
Regarding claim 12 – Chen teaches the manufacturing method of the wiring substrate according to claim 8, wherein an end of the etching barrier layer on the opening section side protrudes toward a center of the opening section, relative to an inner peripheral surface of the opening section.
Parikh teaches wherein an end of the etching barrier layer (fig. 7, 54 [paragraph 0025] Parikh states, “an intermediate layer 54, such as a barrier layer and/or an etch stop, e.g., SiN”) on the opening section side (62/64 [paragraph 0026 & 0033] Parikh states, “vertical interconnect opening 62…undercuts 64”) protrudes toward a center of the opening section (62/64), relative to an inner peripheral surface of the opening section (figure 7 shows the etching barrier layer extending into the opening and overlapping with the opening 62/64).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the manufacturing method of the wiring substrate having an etching barrier layer that extends to an opening section and is flush with the opening section as taught by Chen with the etching barrier layer protrudes towards a center of the opening section relative to an inner peripheral surface of the opening section as taught by Parikh because Parikh states, “the undercuts created by the processes described herein result in a large surface area between the underlying metal feature and the metal deposited in the interconnects. The large surface area between the underlying metal feature and the metal deposited in the interconnects typically decreases the resistance of the device” [paragraph 0042].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tharmarajah et al. (US PG. Pub. 2024/0304536) discloses a high density packaging electromigration protection layer.
Barth et al. (US PG. Pub. 2012/0074574) discloses a semiconductor structure.
Myers et al. (US Patent 5470790) discloses a via hole profile and method of fabrication.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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