DETAILED ACTION
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No. 12,166,083 B2 (hereinafter “Patent 083”). Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter as claimed in the instant application is an obvious variant of the noted claim in Patent 083.
Regarding claim 1, Patent 083 teaches a nitride semiconductor device (“a nitride semiconductor device”) comprising:
a GaN layer (“a GaN layer”);
an AlGaN layer formed on the GaN layer (“an AlGaN layer formed on the GaN layer”);
a plurality of drain contacts and a plurality of source contacts formed over the AlGaN layer, the plurality of drain contacts and the plurality of source contacts arranged alternately in a first direction (“a plurality of drain contacts and a plurality of source contacts formed over the AlGaN layer, the plurality of drain contacts and the plurality of source contacts arranged alternately in a first direction”);
a concave portion formed at an edge portion of the nitride semiconductor device in a cross-section viewed from a second direction orthogonal to the first direction in plan view, a bottom portion of the concave portion formed by the GaN layer (“a concave portion formed at an edge portion of the nitride semiconductor device in a cross-section viewed from a second direction orthogonal to the first direction in plan view, a bottom portion of the concave portion formed by the GaN layer”);
an active region that has a layered structure including the GaN layer and the AlGaN layer (“an active region that has a layered structure including the GaN layer and the AlGaN layer”);
an inactive region that is formed at the layered structure around the active region and that is the concave portion having the bottom portion that reaches the GaN layer (“an inactive region that is formed at the layered structure around the active region and that is the concave portion having the bottom portion that reaches the GaN layer”);
a gate layer that is formed on the AlGaN layer in the active region (“a gate layer that is selectively formed on the AlGaN layer in the active region and that is made of a nitride semiconductor”);
a gate electrode formed on the gate layer (“a gate electrode formed on the gate layer”);
a first insulating film that covers the gate electrode and that is formed on the AlGaN layer in the active region (“a first insulating film that covers the gate electrode and that is in contact with the AlGaN layer in the active region”); and
a second insulating film that covers the first insulating film and that is formed on the inactive region (“a second insulating film that covers the first insulating film and that is in contact with the inactive region”),
wherein the second insulating film is a multi-layer film, the first insulating film is a nitride film, the second insulating film includes a lower layer and an upper layer (“wherein the second insulating film is a multi-layer film, the first insulating film is a nitride film, and the second insulating film includes a layered structure including a nitride film and an oxide film disposed on the nitride film”) (See Patent 083, claim 1).
While Patent 083 does not further teach that the lower layer (“the nitride film”) is thinner than the upper layer (“the oxide film”), it would have been obvious to one of ordinary skill in the art to provide the lower layer thinner than the upper layer as a design choice, for example, in order to provide the lower layer functioning as the liner layer and/or to provide the upper layer functioning as the planarization layer.
Regarding claim 2, Patent 083 teaches further comprising an ohmic electrode that is formed on the first insulating film, that is covered with the second insulating film, and that is ohmically connected to the AlGaN layer through the first insulating film (Patent 083, claim 2).
Regarding claim 3, Patent 083 teaches wherein the ohmic electrode includes each of the source contacts and each of the drain contacts between which the gate electrode is placed (Patent 083, claim 3).
Regarding claim 4, Patent 083 teaches wherein the gate layer is formed in a self-aligned manner with respect to the gate electrode (Patent 083, claim 5).
Regarding claim 5, Patent 083 teaches wherein the concave portion has a depth deeper than a depth position of a two-dimensional electron gas in the layered structure of the active region (Patent 083, claim 6).
Regarding claim 6, Patent 083 teaches wherein the concave portion has a side portion that is tilted with respect to a surface of the AlGaN layer (Patent 083, claim 7).
Regarding claim 7, Patent 083 teaches wherein the first insulating film has an end surface that in continuous with an end surface of the AlGaN layer (Patent 083, claim 8).
Regarding claim 8, Patent 083 teaches wherein a plurality of the gate electrodes are surrounded by the inactive region (Patent 083, claim 9).
Regarding claim 9, Patent 083 teaches wherein the source contact and the drain contact have a rectangle shape in a plan view, and the plurality of the source contacts and the drain contacts are alternately arranged such that long side directions thereof are parallel to each other (Patent 083, claim 4).
Regarding claim 10, Patent 083 teaches wherein the AlGaN layer has a thickness from 10 nm to 20 nm (Patent 083, claim 10).
Regarding claim 11, Patent 083 teaches wherein the first insulating film has a thickness from 90 nm to 110 nm (Patent 083, claim 11).
Regarding claim 12, Patent 083 teaches the upper layer of the second insulating film has a thickness from 0.8 μm to 1.2 μm (Patent 083, claim 12). While Patent does not further teach that the lower layer of the second insulating film has a thickness from 75 nm to 85 nm, it would have been obvious to one of ordinary skill in the art to adjust the thickness of the lower layer by a routine experimentation to obtain the optimal/workable thickness range, including the claimed thickness from 75 nm to 85 nm.
Regarding claim 13, Patent 083 teaches wherein the gate layer is made of a GaN layer doped with an acceptor-type impurity (Patent 083, claim 13).
Regarding claim 14, Patent 083 teaches wherein the bottom portion of the concave portion reaches an end surface of the GaN layer and intersects the end surface of the GaN layer (Patent 083, claim 14).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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