The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 7/7/2026.
Claims 1-3 and 19 are amended.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 7, 2026 has been entered.
Response to Arguments
7. Applicant`s arguments filed July 7, 2026 have been fully considered but they are not persuasive with respect to prior art rejection.
As per the 103 rejection of claim 1, Applicant argued Chen/Jang/ Derzhavetz fails to disclose or suggest the feature of " the flush command comprising a data type field, which includes information on a type of a data unit on which the flush operation is to be performed ", However, Examiner relies on a newly cited references Wolczko to teach these limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 19 are rejected under 35 U.S.C. 103(a) as being disclosed by Chen et al. (US 11,614,478 hereinafter referred to as Chen), and further in view of Jang et al. (US PGPUB 2009/0310412 hereinafter referred to as Jang) in view of Wolczko et al. (US PGPUB 2005/0188186 hereinafter referred to as Wolczko).
As per independent claim 1, Chen discloses a storage device supporting a flush operation among multiple namespaces [(Column 4, lines 41-56 and Column 7, lines 36-56; FIGs. 2 and 6A and related text) wherein Chen teaches where FIG. 2 is a schematic diagram of the namespace table (NST) 112, the index table (IDXT) 114, and a logic-to-physical table (L2PT) 116 in the internal memory 104 and the memory array 106 according to an embodiment of the present invention. In the embodiment of FIG. 2, the NST 112 includes a plurality of namespace identifiers (NSIDs) and at least one internal NSID (i.e., “m-1” of NSID) in first column, and the NST 112 further includes a start entry and an end entry of the IDXT 114 shown as (“start entry”, “end entry”) in second column for each NSIDs and the at least one internal NSID; the processor flushes the latest mapping data in the internal memory 104 not store at the memory array yet to the memory array 106. In step S620, the processor updates the start entry and the end entry of the IDXT 114 (i.e., (0, 0) of mark 651 in part (B) of FIG. 6B) with the narrowed size “1” according to the third NSID “0” in the NST 112, and the processor updates all of the start entry and the end entry of the IDXT 114 (i.e., (1, 1) of mark 652 in part (B) of FIG. 6B). The narrowed size “1” is predetermined by the memory controller, and the narrowed size“1” is smaller than a size between the original entry and the original end entry (0, 1) of the IDXT 112. In step S630, the processor arranges the entries in the IDXT 114 according to the narrowed size “1”. For example, the entry “1” of IDXT 114 in part (A) of FIG. 6B has been deleted, and the original entries “0”, “2”-“4” of IDXT 114 in part (A) of FIG. 6B has been moved to the entries “0”-“3” of IDXT 114 in part (B) of FIG. 6B shown as mark 654. Then, in step S640, the processor flushes flushing latest mapping data in the internal memory not store at the memory array yet to the memory array again to correspond to the claimed limitation], the storage device comprising: a volatile memory configured to temporarily store a plurality of pieces of data received from a host device; a non-volatile memory device comprising a plurality of namespaces [(Column 3, lines 41-46, Column 4, lines 41-56 and Column 7, lines 36-56; FIGs. , 2 and 6A and related text) wherein Chen teaches where the memory device 100 is a storage device. For example, the memory device 100 can be an embedded multimedia card (eMMC), a secure digital (SD) card, a solid-state drive (SSD), or some other suitable storage; FIG. 2 is a schematic diagram of the namespace table (NST) 112, the index table (IDXT) 114, and a logic-to-physical table (L2PT) 116 in the internal memory 104 and the memory array 106 according to an embodiment of the present invention. In the embodiment of FIG. 2, the NST 112 includes a plurality of namespace identifiers (NSIDs) and at least one internal NSID (i.e., “m-1” of NSID) in first column, and the NST 112 further includes a start entry and an end entry of the IDXT 114 shown as (“start entry”, “end entry”) in second column for each NSIDs and the at least one internal NSID; the processor flushes the latest mapping data in the internal memory 104 not store at the memory array yet to the memory array 106. to correspond to the claimed limitation]; and a controller configured to perform a flush operation in response to a flush command received from the host device [(Column 5, lines 60-65, Column 6, lines 30-56 and Column 7, lines 36-56; FIGs. 2 and 6A and related text) wherein Chen teaches where the FIG. 3 is a flow chart illustrating a method for accessing the memory device according to an embodiment of the present invention. Referring to FIG. 1 to FIG. 3, in step S310 of FIG. 3, the memory controller 102 of the memory device 100 obtains the data access command from the host device 101 to determine whether a data of the data access command contains one of the NSIDs, the processor flushes latest mapping data in the internal memory 104 not store at the memory array 106 yet to the memory array 109 to correspond to the claimed limitation], wherein the controller is further configured to, in the flush operation, move at least one piece of data, stored in the volatile memory and corresponding to the flush command, to at least one of the plurality of namespaces of the non-volatile memory device in a unit smaller than or equal to a namespace [(Column 7, lines 36-56; FIG. 6A and related text) wherein Chen teaches where the storage device supporting a flush operation among multiple namespaces, the storage device comprising: a volatile memory configured to temporarily store a plurality of pieces of data received from a host device; a non-volatile memory device comprising a plurality of namespaces; and a controller configured to perform a flush operation in response to a flush command received from the host device, wherein the controller is further configured to, in the flush operation, move at least one piece of data, stored in the volatile memory and corresponding to the flush command, to at least one of the plurality of namespaces of the non-volatile memory device in a unit smaller than or equal to a namespace to correspond to the claimed limitation].
Chen does not appear to explicitly disclose wherein the controller is further configured to, in the flush operation, move at least one piece of data, stored in the volatile memory and corresponding to the flush command, to at least one of the plurality of namespaces of the non-volatile memory device in a unit smaller than or equal to a namespace.
However, Jang discloses wherein the controller is further configured to, in the flush operation, move at least one piece of data, stored in the volatile memory and corresponding to the flush command [(Paragraph 0046; FIGs. 1 and 3) where Jang teaches where FIG. 1 is a block diagram illustrating a data flush operation according to some embodiments. Referring to FIG. 1, an information processing system 10 may include a host 20 and a memory card 50. The memory card 50 responds to a command CMD from the host 20 to store data from the host 20 in a first non-volatile memory module 30. During a flush operation, the memory card 50 rearranges sector data C, 2, A, 1, and B sequentially stored in the first non-volatile memory 30 so as to be divided into groups G1 and G2, and stores the groups G1 and G2 of the sector data in a second non-volatile memory module 40 to correspond to the claimed limitation], to at least one of the plurality of namespaces of the non-volatile memory device in a unit smaller than or equal to a namespace [(Paragraphs 0048, 0050 and 0059; FIGs. 1 and 3) where Jang teaches where sector data C, 2, A, 1, and B input in the first non-volatile memory 30 in a FIFO manner may be divided into groups G1 and G2. The groups G1 and G2 of sector data may be flushed into the second non-volatile memory 40 group-by-group according to a respective priority associated therewith, which may reduce the number of merge operations performed to transfer the data to the second non-volatile memory 40; flush operation may proceed as follows. In the following example, each data block of the second non-volatile memory 150 has 50 sectors. Accordingly, sector data may be grouped by a 50.sup.th unit. In a case where sector data is grouped by a 50.sup.th unit, sector data between a 0.sup.th sector and a 49.sup.th sector may constitute one group. And, sector data between a 50.sup.th sector and a 99.sup.th sector may constitute another group to correspond to the claimed limitation].
Chen and Jang are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Chen and Jang before him or her, to modify the method of Chen to include the flushing of data in a unit smaller than or equal to the namespace of Jang because it will enhance apparatus efficiency.
The motivation for doing so would be [“increase the speed and/or life of a memory system that includes different non-volatile memories; reduce the number of merge operations and/or erase counts below that which may be possible via a host driver of the host 20 or a flash translation layer FTL of a conventional memory card 50” (Paragraphs 0007 and 0048 by Jang)].
Chen does not appear to explicitly disclose the flush command comprising a data type field, which includes information on a type of a data unit on which the flush operation is to be performed.
However, Wolczko discloses the flush command comprising information on a type of a data unit on which the flush operation is to be performed [(Paragraphs 0021-0025) where Wolczko teaches where the history queue 140 is a circular queue of, for example, 128 entries. The history queue 140 enables the processor 100 to provide information which software can then use to reconstruct the flow of execution through the instruction space. The processor 100, and specifically the instruction fetch unit 110, writes to the queue when any of a plurality of control transfer events occur. The control transfer events include, for example, when a control transfer instruction is determined to be taken, when an instruction flush is performed and when an instruction takes a trap. The history queue 140 gathers information for one thread at a time. Using the information in the history queue 140, software can reconstruct a portion of the execution path through the instruction space. The history queue 140 is controlled via a history queue control register 210 which receives an input from, among others, the sampling mechanism 102. Information in the history queue 140 is organized as a plurality of entries, where each entry includes a plurality of fields. More specifically, each entry within the history queue 140 includes a valid field, a program counter field, a privilege state field, a instruction flush field, a instruction flush replay field, a wrap bit field, a flush window identifier field, an instruction taken field, an instruction trap field, a wrap bit field, and a window identifier field; The instruction flush field value indicates that the entry contains information for an instruction flush. The instruction flush replay field is associated with an instruction flush event and indicates that an instruction flush was generated for a mispredicted branch and that the mispredicted branch now resolves not taken; the instruction flush replay field is only defined when the instruction flush value is set. The wrap bit field stores the wrap bit associated with the instruction flush; the wrap bit field value is only defined when the instruction flush value is set. The window identifier field provides the window identifier that is associated with the instruction flush; the window identifier field value only defined when the instruction flush value is set to correspond to the claimed limitation].
Chen and Wolczko are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Chen and Wolczko before him or her, to modify the method of Chen to include the flush command that include identifiers of Wolczko because it will enhance apparatus efficiency.
The motivation for doing so would be [“ensures that the contents are not altered by hardware while software is attempting to read the history queue ” (Paragraph 0029 by Wolczko)].
Therefore, it would have been obvious to combine Chen, Jang and Wolczko to obtain the invention as specified in the instant claim.
As for independent claim 19, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 2-16 and 20, but would be allowable if rewritten in an independent form.
The reasons for allowance of claim 2 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the flush command comprises: a data information field designating the at least one piece of data on which the flush operation is to be performed”.
The reasons for allowance of claim 5 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the non-volatile memory device comprises a first namespace and a second namespace, wherein the volatile memory is configured to store a plurality of pieces of data corresponding to a first stream, and wherein the controller, in response to the flush command for the first stream, is configured to: move at least one piece of data corresponding to the first namespace, among the plurality of pieces of data stored in the volatile memory and corresponding to the first stream, to the first namespace in a unit of a stream smaller than the namespace; and move at least one piece of data corresponding to the second namespace, among the plurality of pieces of data stored in the volatile memory and corresponding to the first stream, to the second namespace in a unit of the stream”.
The reasons for allowance of claim 6 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the non-volatile memory device comprises a first namespace and a second namespace, wherein the volatile memory comprises a first volatile memory and a second volatile memory, and wherein the controller comprises: a first non-volatile memory (NVMe) controller configured to, in response to a first flush command, move at least one piece of data, stored in the first volatile memory, to at least one of the first namespace and the second namespace in the unit smaller than or equal to the namespace; and a second NVMe controller configured to, in response to a second flush command, move at least one piece of data, stored in the second volatile memory, to the second namespace in the unit smaller than or equal to the namespace”.
The reasons for allowance of claim 9 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the non-volatile memory device comprises a first namespace, a second namespace, and a third namespace, wherein the volatile memory comprises a first volatile memory, a second volatile memory, and a third volatile memory, and wherein the controller comprises: a first non-volatile memory (NVMe) controller configured to, in response to a first flush command, move at least one piece of data, stored in the first volatile memory, to the first namespace in the unit smaller than or equal to the namespace; a second NVMe controller configured to, in response to a second flush command, move at least one piece of data, stored in the second volatile memory, to the second namespace in the unit smaller than or equal to the namespace; and a third NVMe controller configured to, in response to a third flush command, move at least one piece of data stored, in the third volatile memory, to the third namespace in the unit smaller than or equal to the namespace”.
The reasons for allowance of claim 14 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the non-volatile memory device comprises a first namespace, a second namespace, and a third namespace, wherein the volatile memory comprises a first volatile memory and a second volatile memory; and wherein the controller comprises: a first non-volatile memory (NVMe) controller configured to, in response to a first flush command, move at least one piece of data stored, in the first volatile memory, to at least one of the first namespace and the second namespace in the unit smaller than or equal to the namespace; and a second NVMe controller configured to, in response to a second flush command, move at least one piece of data, stored in the second volatile memory, to at least one of the second namespace and the third namespace in the unit smaller than or equal to the namespace”.
The reasons for allowance of claim 17 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the controller comprises: a first non-volatile memory (NVMe) controller corresponding to the first namespace and the second namespace and configured to perform a first flush operation and a second flush operation on the first namespace and the second namespace; and a second NVMe controller corresponding to the second namespace and the third namespace and configured to perform a third flush operation and a fourth flush operation on the second namespace and the third namespace, wherein the first NVMe controller, the second NVMe controller, the first namespace, and the third namespace correspond to a first domain, wherein the second namespace corresponds to a second domain, different from the first domain, and wherein a unit of moving the at least one piece of data in the first flush operation and the fourth flush operation corresponding to the first domain is different from a unit of moving the at least one piece of data in the second flush operation and the third flush operation corresponding to the second domain”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED GEBRIL whose telephone number is (571) 270-1857. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135
Prosecution Insights