Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8, 9, 12-16, 18,19, and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (“An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Bb/s”, hereinafter referred to as Kim).
Regarding claim 1, Kim discloses a transmission driver ("For the analysis, a TX test circuit is designed in the 65-nm CMOS process. The test circuit consists of N-over-N driver with a pre-driver and a simplified TSV electrical model with capacitance and resistance [3], as shown in Fig. 2. RTSV and CTSV are the resistance and capacitance of the TSV, respectively, and RSUB is the resistance of silicon substrate between the TSVs.", see Section II. A. and Fig. 2; "Fig. 6 shows the details of the proposed TX. The proposed TX consists of a 4-to-1 MUX with a replica MUX and a pre-driver with an N-over-N main driver, which includes two small sizes of keeper NMOSs. To alleviate the frequency limitation due to the excessive capacitive loading on the output of the 4-to-1 MUX, a 4-to-2 MUX and 2-to-1 MUX with quadrature clock signals are implemented. Since the replica MUX synchronizes the quadrature clock signals to parallel inputs, the timing margin at VDDL, is relaxed. In addition, considering PVT variations, the jitter of MUXOUT is minimized by matching the path delay and balancing loading between the 4-to-2 MUX outputs and clock signals."; see Section III.A. and Fig. 6) for serial communication (see Title and Fig. 6), the transmission driver comprising: first multiplexing circuitry (4-to-2 MUX, Fig. 6) configured to: partially serialize a data group (DO, D1, D2, D3, Fig. 6) into data subgroups (D1/D2, DO/D3, Fig. 6; the data subgroups are explicitly shown at the left-hand side of Fig. 6 as the data streams at the two outputs of the 4-to-2 MUX) based on an in-phase clock (CLKO / CLK180, Fig. 6; the differential in- phase clock CLKO / CLK180 controls the 4-to-2 MUX), and delay (Timing is adjusted by the replica MUX, Fig. 6) a quadrature clock (CLK90 / CLK270, Fig. 6) corresponding to the in-phase clock (CLK0 / CLK180), wherein the delay is based on a latency of the partial serialization ("Since the replica MUX synchronizes the quadrature clock signals to parallel inputs, the timing margin at VDDL is relaxed. In addition, considering PVT variations, the jitter of MUXOUT is minimized by matching the path delay and balancing loading between the 4-to-2 MUX outputs and clock signals.", Section III.A.; the replica 4-to-2 MUX tracks latency delays of the main 4-to-2 MUX across PVT, so that the inputs of the 2-to-1 MUX are synchronized); and second multiplexing circuitry (2-to-1 MUX, Pre-driver w/ Pre-emphasis, N-over-N Driver, Fig. 6) comprising a source- series terminated, SST, driver ("The test circuit consists of N-over-N driver with a pre-driver and a simplified TSV electrical model with capacitance and resistance [3], as shown in Fig. 2." see Section II.A. and Fig. 2; "Fig. 6 shows the details of the proposed TX. The proposed TX consists of a 4-to-1 MUX with a replica MUX and a pre-driver with an N-over-N main driver, which includes two small sizes of keeper NMOSs... The output driver of the proposed TX is composed of the pre-driver and the N-over-N main driver. The pre-driver realizes pre-emphasis (EMP) by increasing its output voltage during the data transition without static power consumption to enable the N-over-N main driver to transmit the signal with the improved SI [signal integrity] through the TSV channel.”, Section III.A and Fig. 6; an N- over-N driver is a voltage-mode driver, i.e. a source-series terminated (SST) driver") configured to serialize the data subgroups (D1/D2, DO/D3, Fig. 6) into a serial data stream (TXOUT, Fig. 6) based on the delayed quadrature clock (CLKR90, CLKR270, Fig. 6).
Regarding claim 2, Kim discloses the transmission driver of claim 1, wherein: the first multiplexing circuitry (4-to-2 MUX) is configured to partially serialize the data group (DO, D1, D2, D3) into the data subgroups (D1/D2, DO/D3) by arranging a four-bit data group (DO, D1, D2, D3, Fig. 6) into a pair of two-bit data groups (D1/D2, DO/D3, Fig. 6); and the second multiplexing circuitry (2-to-1 MUX, Pre-driver w/ Pre-emphasis, N- over-N driver) is configured to serialize the data subgroups (D1/D2, DO/D3) into the serial data stream (TXOUT, Fig. 6) by arranging the pair of two-bit data groups (D1/D2, DO/D3) into the serial data stream (TXOUT, Fig. 6).
Regarding claim 3, Kim discloses the transmission driver of claim 1, wherein the first multiplexing circuitry (4-to-2 MUX) further comprises a unit interval shifter (F/F, L, Fig. 6).
Regarding claim 4, Kim discloses the transmission driver of claim 3, wherein the unit interval shifter is configured to delay a time when bits of the data group are partially serialized (the bitstream through the lower F/F, L path controlled by CLKO and CLK180 is delayed with respect to the upper F/F path by 180° of the quarter-rate clock, which corresponds to two UI of the output data stream at TXOUT, Fig. 6).
Regarding claim 5, Kim discloses the transmission driver of claim 1, wherein the SST driver (N-over-N driver) comprises a first transistor (upper Small NMOS of the N-over-N driver driven by PUHOLD, Fig. 6) and a second transistor (lower Small NMOS of the N-over-N driver driven by PDHOLD, Fig. 6) to serialize the data subgroups into the serial data stream based on the delayed quadrature clock.
Regarding claim 6, Kim discloses the transmission driver of claim 5, further comprising a first logic gate (upper input NAND gate of the 2-to-1 MUX, Fig. 6) and a second logic gate (lower input NAND gate of the 2-to-1 MUX, Fig. 6) configured to respectively control the first transistor and the second transistor (both NAND gates control both transistors), wherein: the first logic gate and the second logic gate are coupled between the first multiplexing circuitry (4-to-2 MUX) and the second multiplexing circuitry (2-to-1 MUX, Pre-driver w/ Pre-emphasis, N-over-N driver); a gate of the first transistor is coupled to an output of the first logic gate (the gates of the upper NMOS transistors of the N-over-N driver are coupled via the output gate of the 2-to-1 MUX and the Pre-driver to the upper input NAND gate of the 2-to-1 MUX, Fig. 6); and a gate of the second transistor is coupled to an output of the second logic gate (the gates of the lower NMOS transistors of the N-over-N driver are coupled via the output gate of the 2-to-1 MUX and the Pre-driver to the lower input NAND gate of the 2-to-1 MUX, Fig. 6).
Regarding claim 8, Kim discloses the transmission driver of claim 6, wherein: the SST driver (N-over-N driver) further comprises a third transistor (upper NMOS transistor of the N-over-N driver driven by PUEMP, Fig. 6) and a fourth transistor (lower NMOS transistor of the N-over-N driver driven by PDEMP, Fig. 6) to serialize the data subgroups (D7/D2, DO/D3) into the serial data stream (TXOUT, Fig. 6) based on the delayed quadrature clock (CLKR90, CLKR270, Fig. 6), wherein: the third transistor has the same source and drain connections as the first transistor (see Fig. 6), and the fourth transistor has the same source and drain connections as the second transistor (see Fig. 6); and the transmission driver further comprises a third logic gate (the PUEMP control signal is generated by the Pre-driver, which comprises at least one inverter between its input and its output, Figs. 6 and 8) and a fourth logic gate (the PDEMP control signal is generated by the Pre-driver, which comprises at least one inverter between its input and its output, Figs. 6 and 8) configured to respectively control the third transistor and the fourth transistor.
Regarding claim 9, Kim discloses the transmission driver of claim 6, wherein a shared pair of inputs (output of 4-to-2 MUX) is provided to the first logic gate and the second logic gate.
Method claims 12-16, 18, and 19 are essentially the same in scope as apparatus claims 1-6, 8, and 9 and are rejected similarly.
Claim 22 is essentially the same in scope as claims 5 and 6 and is rejected similarly.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding claims 7 and 17, Kim discloses all the features and limitations as discussed above and further disclose wherein the first logic gate is a NAND gate but does not disclose the second logic gate is a NOR gate. Kim discloses a NAND gate instead.
However, it is well known in the art that NAND, NOR, AND, or OR logic gates are interchangeable by inverting the signals at the output or inputs of the logic gate by De Morgan's theorem.
Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to substitute the well-known NAND gate of Kim with a NOR gate as taught by De Morgan' s theorem. It is merely a matter of obvious engineering choice.
Claim(s) 11 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bulzacchelli et al. (“A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology”, hereinafter referred to as Bulzacchelli).
Regarding claims 11 and 21, Kim discloses all the features and limitations as discussed above but does not explicitly disclose wherein the SST driver further comprises at least one impedance-tuning transistor configured to control an impedance associated with transmitting the serial communication.
Bulzacchelli disclose the SST driver which comprises at least one impedance-tuning transistor configured to control an impedance associated with transmitting the serial communication (Fig. 3).
Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features of Bulzacchelli into the device of Kim to adjust the SST driver's output resistance to match the transmission line's characteristic impedance as taught by Bulzacchelli.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 5712728048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL D CHANG/ Primary Examiner, Art Unit 2844