Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Claim 9, lines 11 recites the limitation “a path”. It is unclear whether the path is the same path as the path in claim 4 line 3 or a different path. Therefore, the claim has an indefinite scope. Furthermore, claim 9, recites the limitation “the third switch” in line 17. There is insufficient antecedent basis for these limitations in the claim.
In claims 9, lines 33, 36, and 39, and claim 10, lines 3, 6, 9, and 12, in each claim, recites the limitation “a resistive circuit element”, it is unclear whether the resistive circuits are the same resistive circuit element in claim 9, line 30, or additional resistive circuit elements. Therefore, the claims have an indefinite scope.
Claim Objections
Claims 2 and 9 are objected to because of the following informalities:
In claim 2, line 2, and claim 9, lines 26-27, in each claim, “the bias voltage” should read as --the direct-current bias voltage--, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over SAWADA (US 20210288679 A1) in view of Brindle (US 20110169550 A1) and Scott (US 10447344 B2), hereafter referred to as “SAWADA”, “Brindle”, and “Scott”, respectively.
Regarding claims 1-8 and 11 , in the embodiment of Fig. 1, SAWADA discloses:
A communication device (communication device 5) comprising:
a radio-frequency (RF) signal processing circuit (Fig. 1, radio frequency (RF) signal processing circuit (RF integrated circuit (RFIC)) 3) configured to process radio-frequency signals amplified, or to be amplified, by the amplifier circuit (RFIC 3 processes radio frequency signals transmitted and received, per claim 11); and
an amplifier circuit (radio frequency module 1) comprising:
a first input terminal (antenna connection terminal 100) configured to receive a radio-frequency signal (via antenna 2);
an amplifier (low noise amplifier 20) configured to amplify the radio-frequency signal, wherein the amplifier is a low-noise amplifier (low noise amplifier 20) configured to amplify a receive signal from the first input terminal (reception signal is passed from terminal 100 to low noise amplifier 20 via filters 30R and 40R per paragraph [0038] per claim 5);
a switching circuit (switch 52) coupled between the amplifier and the first input terminal (as shown in Fig. 1), wherein an acoustic wave filter (reception filters 30R and 40R can be acoustic wave filters per paragraph [0053]) coupled between the first input terminal and the switching circuit (as shown in Fig. 1 per claim 6), further comprising an inductor (matching circuit 64 of Fig. 1 is shown to be a single inductor in analogous matching circuit 64 in Fig. 6A and per paragraph [0148]) having a first end coupled to an input end of the amplifier and a second end coupled to the first terminal,wherein there is no inductor between ground and a path connecting the input end of the amplifier and the first terminal (matching circuit 64 is disposed on reception paths that connect low noise amplifier 20 and reception filters 30R and 40R per paragraph [0042], and connected to terminal 100 per paragraph [0038], per claim 7); and a bias circuit (PA control circuit 80) configured to supply a direct-current bias voltage (PA control circuit 80 outputs bias voltage to amplifying elements),
wherein the switching circuit comprises:
a first terminal (right terminal of switch 52 connected to element 64, as per claim 2) coupled to the amplifier (via element 64), and a second terminal (left terminal of switch 52) coupled to the first input terminal (per paragraph [0055] lines 6-11), and a first switch (switch 52, as per claims 3, 4, and 8).
However, SAWADA is silent in teaching the bias circuit configured to supply the direct-current bias voltage to the amplifier and the first substrate through the amplifier and first terminal, and
the first switch comprises a first transistor that has a first control terminal and a first substrate of at least a first conductivity type, the first switch being configured to selectively connect the first terminal and the second terminal in response to a voltage applied to the first control terminal, and
wherein the bias circuit, the first terminal, and the first substrate are coupled for direct-current conduction, and
wherein the first substrate has a first region of a second conductivity type coupled to the first terminal and a second region of the second conductivity type coupled to the second terminal,
wherein the first switch comprises a field-effect transistor,
wherein the first region is a source region, and the second region is a drain region,
wherein the first control terminal is a gate terminal, and
wherein the first region is coupled to the first substrate,
a second switch coupled between ground and a path connecting the first switch and the second terminal, and
wherein the switching circuit further comprises:
a plurality of the first switches, each coupled in series between the first terminal and the second terminal, and
a plurality of the second switches, each coupled in series between ground and the path connecting the first terminal and the second terminal, and
wherein among the plurality of first switches and the plurality of second switches, any of the plurality of first switches is coupled closest to the amplifier.
Brindle and Scott teaches:
the first switch comprises a first transistor (Brindle, Fig. 5A, switching SOI MOSFET 506, Note RF switches are implemented using SOI MOSFETS of Fig. 1, per paragraph [0067]) that has a first control terminal (506 gate (Gate 108 in Fig. 1)) and a first substrate (Fig. 1, Body 114 and/or insulating substrate 118) of at least a first conductivity type (body 114 comprises a P- region (i.e., a region that is lightly doped with a "p-type" dopant), produced by ion implantation, or by dopants already present in the silicon layer when it is formed on the insulating substrate 118, per paragraph [0007] lines 14-18), the first switch being configured to selectively connect the first terminal and the second terminal in response to a voltage applied to the first control terminal (Scott, Fig. 3A, body (i.e. substrate) of transistor F is coupled to its drain and source via Ssb and Sdb switches, wherein a high gate voltage of FET F switches Ssb and Sdb on, thereby connected the drain and source of transistor F to its body, per column 7 lines 58-60), and wherein the bias circuit, the first terminal, and the first substrate are coupled for direct-current conduction (Scott, Proper operation requires that each FET has direct current bias on its terminals per column 1 lines 25-29), and wherein the first substrate has a first region (Brindle, source 112) of a second conductivity type (n-type, source 112 and drain 116 are doped with “n-type” material, per [0007] lines 8-11) coupled to the first terminal and a second region (drain 116) of the second conductivity type (n-type, per [0007] lines 8-11) coupled to the second terminal, wherein the first switch comprises a field-effect transistor (Brindle, per paragraph [0003]), wherein the first region is a source region and the second region is a drain region (Brindle, source 112 and drain 116, as previously shown in Fig. 1), wherein the first control terminal is a gate terminal (Brindle, gate 108, as shown in Fig. 1), and wherein the first region is coupled to the first substrate (Brindle, as shown in Fig. 1), a second switch (Brindle, Fig. 5A, shunting SOI NMOSFET 508) coupled between ground and a path connecting the first switch and the second terminal (508 is shown coupled between ground and input terminal 502), and wherein the switching circuit further comprises:
a plurality of the first switches (Brindle, Fig. 6, SOI NMOSFETs 602, 604 and 606 in RF switch circuit 600), each coupled in series between the first terminal and the second terminal (coupled in series between terminals 504 and 502, as shown in Fig. 6), and a plurality of the second switches (Brindle, ACC SOI NMOSFETs 620, 622 and 624), each coupled in series between ground and the path connecting the first terminal and the second terminal (as shown in Fig. 6, connected between ground and between terminals 502 and 504), and wherein among the plurality of first switches and the plurality of second switches, any of the plurality of first switches is coupled closest to the amplifier (NMOSFETs 620, 622 and 624 are coupled to output terminal 504, which functions as the first terminal).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have replaced the generic switch in SAWADA (fig. 1) with the switch configurations taught by Brindle (Figs. 1, 5A, and 6) to improve circuit performance (paragraph [0153] lines 13-16), thereby suggesting the obviousness of such a combination. It would be further obvious for the switches substrate as taught in Brindle (Fig. 1) to be connected to the bias circuit and terminal as taught by Scott (Fig. 3A) to control the states of the transistor (column 1, lines 30-32), thereby suggesting the obviousness of such a combination. Furthermore, it would be obvious to modify the amplifier by the resultant combination of Brindle and Scott (Brindle, Figs. 5A and 6 and Scott, Fig. 3A), to further include a bias circuit to supply the direct-current bias voltage to the amplifier, such as the bias circuit taught by SAWADA (Fig. 1) to adjusts the gain of amplifying elements (per paragraph [0028], lines 7-12), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 9-10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 9 and 10:
the cited prior art of record, SAWADA (US 20210288679 A1), either singly or in proper combination, does not teach or make obvious, along with the other claimed features,
“wherein one of the plurality of first switches comprises a resistive circuit element coupling the first region and the second region, wherein another of the plurality of first switches does not comprise a resistive circuit element coupling the first region and the second region, wherein one of the one or more third switches comprises a resistive circuit element coupling the third region and the fourth region, and wherein another of the one or more third switches does not comprise a resistive circuit element coupling the third region and the fourth region” per claim 9.
Claim 10 is objected to as being dependent on claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
Prosecution Insights