DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites an FS/2 and FS/4 frequency clock. The use of FS is indefinite because it is merely an undefined variable and it is unclear how it further limits the functions of the frequency doubler. By definition, a frequency doubler outputs a signal at double the frequency of an input signal. The value of FS/2 is self-evidently twice the value of FS/4, so it is unclear how the inclusion of the values FS, FS/2, and FS/4 further limits the function of the frequency doubler without any further definition of FS. FS could therefore be reasonably interpreted as a placeholder for any arbitrary value, with FS/2 and FS/4 being arbitrary values by extension.
Claims 10 and 14 are rejected on the same basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Parvizi et al., U.S. Patent Application Publication No. 2022/0171425, in view of Lu et al., U.S. Patent No. 12,517,546.
Regarding claim 1, Parvizi discloses a circuit comprising:
a differential frequency doubler [Fig. 2: DFD 2120] configured to generate a differential FS/2 frequency clock [Differential FS/2 distribution 2200] from a differential FS/4 frequency clock [output of FS/4 PLL] using two clock phases as inputs [Fig. 5: DFD receives two differential FS/X clocks as inputs].
Parvizi does not disclose a multistage clock driver configured to correct asymmetry.
Lu discloses a multistage clock driver configured to at least correct asymmetry [Fig. 1 vs. Fig. 4: skew introduces asymmetry in differential clocks] of a differential clock [Fig. 8: skew correction circuit; col. 9, lines 28-39: “The first skew correction circuits 724, 726 detects skew of a corresponding one of the pairs of pseudo-differential complementary clock signals clktp2, clktn2 and adjusts delay of received pseudo-differential complementary clock signals clktp1, clktn1 output from the first skew correction circuits 724, 726 to minimize and/or eliminate the skew. This results in aligned pseudo-differential complementary clock signals clktp2, clktn2, which are provided to the transmitters 706, 708. The transmitters 706, 708 implement CMOS signaling to transmit data based on the aligned pseudo-differential complementary clock signals clktp2, clktn2.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Parvizi and Lu by modifying Parvizi to include the multistage clock driver of Lu. Both Parvizi and Lu are directed to inventions that distribute differential clocks for high speed applications. Lu teaches that skew in differential clock signals can have a negative impact on timing of component operations and detection of signal transitions [col. 8, lines 31-34], and discloses a circuit for correcting skew. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Lu to Parvizi based on Lu’s teachings that skew in differential clock signals negatively impacts performance, and also Lu’s teaching of a mechanism for correcting skew.
Claim 10 recites a method executing the same functions as the circuit of claim 1, and is rejected on the same basis.
Allowable Subject Matter
Claims 14-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claims 2-9 and 11-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Saputra et al., U.S. Patent Application Publication No. 2025/0211218, discloses a circuit for correcting skew in a single-ended to differential clock signal conversion circuit [Fig. 5, para. 0053].
Khan et al., U.S. Patent Application Publication No. 2024/0339996, discloses a clock doubler circuit [Fig. 2].
Jiang et al., U.S. Patent Application Publication No. 2022/0190848, discloses a frequency doubler and a circuit to adjust the symmetry of the frequency doubler output [para. 0162, Fig. 16].
Clara, U.S. Patent Application Publication No. 2017/0237419, discloses a circuit that receives a differential clock and compensates for skew at the input of a DAC [para. 0026].
Li et al., U.S. Patent Application Publication No. 2010/0301913, discloses a circuit corrects duty cycles in a differential input clock and thereby corrects its symmetry [para. 0004, Fig. 3 and 4].
Dreps et al., U.S. Patent Application Publication No. 2006/0181320, discloses a duty cycle adjustment circuit to correct for asymmetry in a differential clock signal [abstract].
Strom, U.S. Patent No. 6,066,972, discloses a circuit for correcting asymmetry in a differential clock signal [abstract].
Anderson, U.S. Patent No. 5,864,246, discloses a differential clock doubler circuit [Fig. 4 and 5].
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
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