DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 11/01/2024 has been considered and placed of record in the file.
Oath/Declaration
The Oath or Declaration is being considered by examiner and complies with PTO requirements.
Claim Objections
Claims 1, 6 and 10-11 are objected to because of the following informalities:
Regarding claim 1, “the I-Q merged phase interpolator comprises,” should be changed to -- the I-Q merged phase interpolator comprises: -- in line 12.
Regarding claim 6, define “CML2CMOS” in line 5 and line 7.
Regarding claim 10, “a plurality of output nodes” should be changed to – the plurality of output nodes – in lines 3-4.
Regarding claim 11, “including,” should be changed to -- including: -- in line 5; and “the the I clock signal” should be changed to – the I clock signal – in line 11.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2 of U.S. Patent No. 12,155,743. Although the claims at issue are not identical, they are not patentably distinct from each other because
Patent Application #18/934,842
Patent #12,155,743
Claim 1: A clock data recovery circuit comprising:
an inphase-quadrature (I-Q) merged phase interpolator configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, a first clock pair comprising an I clock signal and an inverted I clock signal and a second clock pair comprising a Q clock signal and an inverted Q clock signal;
a sampler configured to sample input data using the first clock pair and the second clock pair; and
a control circuit configured to provide a control signal, to the I-Q merged phase interpolator, for controlling phases of the first clock pair and the second clock pair based on a sampling result of the sampler,
wherein the I-Q merged phase interpolator comprises,
a first phase mixer configured to generate the first clock pair,
a second phase mixer configured to generate the second clock pair, and
the first and second phase mixers are configured to share analog inputs based on the control signal.
Claim 1: A clock data recovery circuit comprising:
an inphase-quadrature (I-Q) merged phase interpolator circuit, the I-Q merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals, the plurality of reference clock signals having different phases, the first clock pair comprising an I clock signal and an inverted I clock signal, and the second clock pair comprising a Q clock signal and an inverted Q clock signal;
a sampler circuit configured to sample input data based on the first clock pair and the second clock pair; and
a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit,
the I-Q merged phase interpolator circuit including an I-phase mixer and a Q-phase mixer
wherein the I-Q merged phase interpolator circuit is further configured to, share analog inputs between the I-phase mixer and the Q-phase mixer based on the control signal, the sharing the analog inputs including outputting a current as the analog inputs through at least one activated path among a plurality of paths based on the control signal.
Claim 2: The clock data recovery circuit of claim 1, wherein the I-Q merged phase interpolator further comprises:
a decoder configured to generate a phase interpolation code from the control signal;
and a current steering digital to analog converter (DAC) configured to generate the analog inputs based on the phase interpolation code.
Claim 2: The clock data recovery circuit of claim 1, wherein the I-Q merged phase interpolator circuit is further configured to: generate a phase interpolation code from the control signal; and
generate the analog inputs based on the phase interpolation code.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. US 11,849,015 in view of Hissen et al. US 7,363,563.
Consider claim 1, Zhao discloses A clock data recovery circuit (see FIG. 1) comprising:
an inphase-quadrature (I-Q) merged phase interpolator configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals (see FIG. 1 and col 5 lines 30-36, wherein phase interpolator 100 i.e. inphase-quadrature (I-Q) merged phase interpolator, configured to generate a first clock pair i.e. clk’0 and clk’180, and a second clock pair i.e. clk’90 and clk’270, from a plurality of reference clock signals i.e. clk0, clk90, clk180, and clk270), the plurality of reference clock signals having different phases (see col. 5 lines 27-30, wherein the PLL 152 provides clock 109 having four phases), a first clock pair comprising an I clock signal and an inverted I clock signal (see col. 5 lines 33-36, wherein the first clock pair comprises an I clock signal i.e. clk’0, and an inverted I clock signal i.e. clk’180) and a second clock pair comprising a Q clock signal and an inverted Q clock signal (see col. 5 lines 33-36, wherein the second clock pair comprises a Q clock signal i.e. clk’90, and an inverted Q clock signal i.e. clk’270);
a sampler configured to sample input data using the first clock pair and the second clock pair (see FIG. 1 and col. 5 lines 36-39, wherein sampler 155 samples incoming data 156 using the first clock pair i.e. clk’0 and clk’180, and the second clock pair i.e. clk’90 and clk’270); and
a control circuit configured to provide a control signal, to the I-Q merged phase interpolator, for controlling phases of the first clock pair and the second clock pair based on a sampling result of the sampler (see FIG. 1 and col. 5 lines 36-44, wherein phase interpolator controller 159 output phase code signal 111 to the phase interpolator 100 to control the phases of the first clock pair and the second clock pair).
However Zhao does not explicitly disclose wherein the I-Q merged phase interpolator comprises: a first phase mixer configured to generate the first clock pair, a second phase mixer configured to generate the second clock pair, and the first and second phase mixers are configured to share analog inputs based on the control signal. Hissen teaches wherein the I-Q merged phase interpolator (see FIG. 11, phase interpolator 1002) comprises: a first phase mixer configured to generate the first clock pair (see FIG. 11, col. 10 lines 62-64 and col. 12 lines 63-65, wherein first phase mixer i.e. mixer 1120 and/or 1122, configured to generate first clock pair), a second phase mixer configured to generate the second clock pair (see FIG. 11, col. 10 lines 62-64 and col. 12 lines 63-65, wherein second phase mixer i.e. mixer 1124 and/or 1126, configured to generate second clock pair), and the first and second phase mixers are configured to share analog inputs based on the control signal (see FIG. 10-11, col. 11 lines 49-60, wherein the mixers 1120, 1122, 1124, and 1126 are configured to share analog inputs i.e. thermometer codes output from DAC code, based on the control signal output from phase control circuit 1006). Hissen further discloses maintaining the jitter performance of the high-speed communications device and do not add jitter to the transmitted data during normal operational mode (see col. 3 lines 65-67). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Zhao, and to include wherein the I-Q merged phase interpolator comprises: a first phase mixer configured to generate the first clock pair, a second phase mixer configured to generate the second clock pair, and the first and second phase mixers are configured to share analog inputs based on the control signal, as taught by Hissen for the purpose of maintaining the jitter performance of the high-speed communications device and do not add jitter to the transmitted data during normal operational mode.
Consider claim 8, Zhao discloses A clock data recovery circuit comprising:
an inphase-quadrature (I-Q) merged phase interpolator circuit configured to generate a first clock pair and a second clock pair from a plurality of reference clock signals (see FIG. 1 and col 5 lines 30-36, wherein phase interpolator 100 i.e. inphase-quadrature (I-Q) merged phase interpolator, configured to generate a first clock pair i.e. clk’0 and clk’180, and a second clock pair i.e. clk’90 and clk’270, from a plurality of reference clock signals i.e. clk0, clk90, clk180, and clk270), the plurality of reference clock signals having different phases (see col. 5 lines 27-30, wherein the PLL 152 provides clock 109 having four phases), a first clock pair comprising an I clock signal and an inverted I clock signal (see col. 5 lines 33-36, wherein the first clock pair comprises an I clock signal i.e. clk’0, and an inverted I clock signal i.e. clk’180) and a second clock pair comprising a Q clock signal and an inverted Q clock signal (see col. 5 lines 33-36, wherein the second clock pair comprises a Q clock signal i.e. clk’90, and an inverted Q clock signal i.e. clk’270);
a sampler circuit configured to sample input data using the first clock pair and the second clock pair (see FIG. 1 and col. 5 lines 36-39, wherein sampler 155 samples incoming data 156 using the first clock pair i.e. clk’0 and clk’180, and the second clock pair i.e. clk’90 and clk’270); and
a control circuit configured to control phases of the first clock pair and the second clock pair, the controlling including providing a control signal to the I-Q merged phase interpolator circuit based on a sampling result of the sampler circuit (see FIG. 1 and col. 5 lines 36-44, wherein phase interpolator controller 159 output phase code signal 111 to the phase interpolator 100 to control the phases of the first clock pair and the second clock pair),
wherein the I-Q merged phase interpolator includes: a decoder configured to generate a phase interpolation code from the control signal (see FIG. 3, and col. 6 lines 10-15, wherein the binary-to-thermometer decoder 201 generates phase interpolation code i.e. THERM [7:0] and THERMB [7:0]).
However Zhao does not explicitly disclose wherein the I-Q merged phase interpolator includes: a plurality of digital to analog converting (DAC) circuits configured to generate a plurality of analog inputs based on the phase interpolation code and coupled in parallel with each other to share a plurality of output nodes outputting the plurality of analog inputs, and a plurality of phase mixers configured to commonly receive the plurality of analog inputs from the plurality of output nodes and to generate the first clock pair and the second clock pair based on the plurality of analog inputs. Hissen teaches wherein the I-Q merged phase interpolator (see FIG. 11) includes: a plurality of digital to analog converting (DAC) circuits (see FIG. 11, DAC code 1104, DAC , and 1108) configured to generate a plurality of analog inputs based on the phase interpolation code (see FIG. 11 and col. 11 lines 50-62, wherein the DAC code 1104, DAC 1106, and 1108 configured to generate plurality of analog inputs based on the phase interpolation code output from the phase control circuit 1006) and coupled in parallel with each other to share a plurality of output nodes outputting the plurality of analog inputs (see FIG. 11, wherein DAC 1106 and 1108 are coupled in parallel with each other to share a plurality of output nodes outputting the plurality of analog inputs), and a plurality of phase mixers (see FIG. 11, mixers 1120, 1122, 1124, and 1126) configured to commonly receive the plurality of analog inputs from the plurality of output nodes and to generate the first clock pair and the second clock pair based on the plurality of analog inputs (see FIG. 10-11, col. 11 lines 49-60, wherein the mixers 1120, 1122, 1124, and 1126 are configured to commonly receive the plurality of analog inputs i.e. outputs from DAC 1104, 1106, and 1108, and generate first clock pair and the second clock pair signal). Hissen further discloses maintaining the jitter performance of the high-speed communications device and do not add jitter to the transmitted data during normal operational mode (see col. 3 lines 65-67). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Zhao, and to include wherein the I-Q merged phase interpolator includes: a plurality of digital to analog converting (DAC) circuits configured to generate a plurality of analog inputs based on the phase interpolation code and coupled in parallel with each other to share a plurality of output nodes outputting the plurality of analog inputs, and a plurality of phase mixers configured to commonly receive the plurality of analog inputs from the plurality of output nodes and to generate the first clock pair and the second clock pair based on the plurality of analog inputs, as taught by Hissen for the purpose of maintaining the jitter performance of the high-speed communications device and do not add jitter to the transmitted data during normal operational mode.
Consider claim 2, Zhao discloses wherein the I-Q merged phase interpolator further comprises: a decoder configured to generate a phase interpolation code from the control signal (see FIG. 3 and col. 6 lines 10-15, wherein the binary-to-thermometer decoder 201 generates phase interpolation code i.e. THERM [7:0] and THERMB [7:0]). Hissen discloses a current steering digital to analog converter (DAC) configured to generate the analog inputs based on the phase interpolation code (see FIG. 11, col. 11 lines 52-62, wherein DAC code circuit 1104 output analog inputs based on the phase interpolation code i.e. thermometer-coded control words).
Consider claim 4, Hissen discloses wherein the first phase mixer comprises first output circuits configured to output the analog inputs as the first clock pair in response to the plurality of reference clock signals (see FIG. 11, wherein mixers 1120 and 1122 outputs the analog inputs as the first clock pair in response to the plurality of reference clock signals); and the second phase mixer comprises second output circuits configured to output the analog inputs as the second clock pair in response (see FIG. 11, wherein mixers 1124 and 1124 outputs the analog inputs as the second clock pair in response to the plurality of reference clock signals).
Claim(s) 11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hissen et al. US 7,363,563 in view of Zhao et al. US 11,849,015.
Consider claim 11, Hissen discloses An apparatus (see FIG. 2) comprising:
a receiving circuit (see FIG. 2, receiver 206); and
a transmitting circuit configured to transmit input data to the receiving circuit through a channel (see FIG. 2 and col. 1 lines 37-40, transmitter 204 configured to transmit input data to the receiving circuit through transmission line),
wherein the receiving circuit comprises a clock data recovery circuit (see FIG. 2, clock recovery unit 216) including,
an inphase-quadrature (I-Q) merged phase interpolator circuit (see FIG. 10-11, phase interpolator 1002) configured to generate analog inputs based on a phase interpolation code and receive the analog inputs to generate clock signal (see FIG. 10-11 and col. 11 lines 49-55, wherein the phase interpolator 1002 generate analog inputs i.e. outputs from DAC 1104, 1106, and 1108, based on phase interpolator code i.e. thermometer-code control words, and generate clock signal i.e. async clock).
However Hissen does not explicitly disclose phase interpolator generates an I clock signal, an inverted I clock signal, a Q clock signal, and an inverted Q clock; a sampler circuit configured to sample input data based on the I clock signal, the inverted I clock signal, the Q clock signal, and the inverted Q clock signal, and a control circuit configured to control phases of the I clock signal, the inverted I clock signal, the Q clock signal based on a sampling result of the sampler circuit. Zhao teaches phase interpolator generates an I clock signal, an inverted I clock signal, a Q clock signal, and an inverted Q clock (see FIG. 1 and col. 5 lines 33-36, wherein phase interpolator 100 generates an I clock signal i.e. clk’0, an inverted I clock signal i.e. clk’180, a Q clock signal i.e. clk’90, and an inverted Q clock signal i.e. clk’270); a sampler circuit configured to sample input data based on the I clock signal, the inverted I clock signal, the Q clock signal, and the inverted Q clock signal (see FIG. 1 and col. 5 lines 36-39, wherein sampler 155 samples input data i.e. DATA_IN 156 based on the interpolated clock signal 108 i.e. clk’0, clk’90, clk’180, and clk’270), and a control circuit configured to control phases of the I clock signal, the inverted I clock signal, the Q clock signal based on a sampling result of the sampler circuit (see FIG. 1 and col. 5 lines 42-44 and lines 56-65, wherein phase interpolator controller 159 outputs PH_code to control the phase rotation direction of the interpolated clock signal 108). Zhao further discloses providing phase interpolation circuitry that accommodates interpolation among an arbitrary number of clock phases (see col. 1 lines 15-28). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the invention of Hissen, and to include phase interpolator generates an I clock signal, an inverted I clock signal, a Q clock signal, and an inverted Q clock; a sampler circuit configured to sample input data based on the I clock signal, the inverted I clock signal, the Q clock signal, and the inverted Q clock signal, and a control circuit configured to control phases of the I clock signal, the inverted I clock signal, the Q clock signal based on a sampling result of the sampler circuit, as taught by Zhao for the purpose of providing phase interpolation circuitry that accommodates interpolation among an arbitrary number of clock phases.
Consider claim 14, Hissen discloses wherein output nodes of the I-Q merged phase interpolator circuit are shared by a plurality of phase mixers (see FIG. 11, mixers 1120, 1122, 1124, and 1126).
Allowable Subject Matter
Claims 3, 5-7, 9-10, 12-13, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JANICE N TIEU/Primary Examiner, Art Unit 2633