DETAILED ACTION
This office action is in response to the application filed on 11/1/24.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 4, 16 and 19 are objected to because of the following informalities:
In regards to claims 4, 16 and 19, it appears that “the sum” should be “a sum”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-22 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Zou (US20220057855).
Regarding Claim 1, Zou discloses an integrated circuit (fig. 1-6), comprising: a switching control pin configured to receive a control signal (PWM); a first power unit (120A) having at least one power switch (H/S FET, L/S FET); a second power unit (120B) having at least one power switch (H/S FET, L/S FET); and a driving control circuit (110) configured to provide a first driving signal (121A output to H/S FET) to the first power unit in response to the control signal, and to provide a second driving signal (121B output to H/S FET) to the second power unit in response to the control signal; wherein the first power unit is turned on to perform a switching operation and the second power unit is turned off under a first load condition (light load, ¶21, 22), and both the first power unit and the second power unit are turned on to perform a switching operation under a second load condition (normal load, ¶42).
Regarding Claim 2, Zou discloses (fig. 1-6) each of the first power unit and the second power unit comprises: a first switch (HS FET) having a first terminal (@VDD), a second terminal (@410) and a control terminal (gate), wherein the first terminal of the first switch is configured to receive an input voltage (VDD); and a second switch (LS FET) having a first terminal (@410), a second terminal (@GND) and a control terminal (gate), wherein the first terminal of the second switch is coupled to the second terminal of the first switch (@410), and the second terminal of the second switch is configured to be coupled to a reference voltage level (GND).
Regarding Claim 3, Zou discloses (fig. 1-6) an output pin (@ L) configured to provide a phase current for a multiphase voltage regulator, wherein the output pin is coupled to the first terminal of the second switch of the first power unit and the first terminal of the second switch of the second power unit (Ls are commonly connected).
Regarding Claim 4, Zou discloses (fig. 1-6) a first output pin coupled to the first terminal of the second switch of the first power unit, wherein the first output pin is configured to provide a first current (@L); and a second output pin coupled to the first terminal of the second switch of the second power unit, wherein the second output pin is configured to provide a second current (@L); wherein the sum of the first current and the second current is a phase current for a multiphase voltage regulator (¶19).
Regarding Claim 5, Zou discloses (fig. 1-6) the control signal indicates a power mode (¶47).
Regarding Claim 6, Zou discloses (fig. 1-6) the control signal indicates a load condition (¶47).
Regarding Claim 7, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; wherein the first power unit is turned on and the second power unit is turned off when the mode command indicates a light load condition (ENABLE, ¶21, 22).
Regarding Claim 8, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command; wherein the first power unit and the second power unit are turned on to perform a switching operation when the mode command indicates a heavy load condition (ENABLE, ¶42).
Regarding Claim 9, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit is turned on to perform a switching operation and the second power unit is turned off when the mode command indicates a discontinuous conduction mode (DCM) operation (¶27).
Regarding Claim 10, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit and the second power unit are turned on to perform a switching operation when the mode command indicates a continuous conduction mode (CCM) operation (¶37, 60).
Regarding Claim 11, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit is turned on to perform a switching operation and the second power unit is turned off when the mode command indicates a single phase operation (¶21).
Regarding Claim 12, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit and the second power unit are turned on to perform a switching operation when the mode command indicates a full phase operation (¶42).
Regarding Claim 13, Zou discloses an integrated circuit (fig. 1-6), comprising: a switching control pin configured to receive a control signal (PWM); a mode pin configured to receive a mode command (DRON, ¶49); a first power unit having a first current capability; a second power unit having a second current capability, wherein the second current capability is greater than the first current capability (table 1 shows different enablement modes with different current capabilities); a driving control circuit (110) configured to provide a first driving signal (121A output to H/S FET) to the first power unit in response to the control signal and the mode command, and to provide a second driving signal (121B output to H/S FET) to the second power unit in response to the control signal and the mode command; wherein the first power unit is located in a first region and the second power unit is located in a second region (locations) ; wherein each of the first power unit and the second power unit comprises: a first switch (H/S Fet) having a first terminal (@VDD), a second terminal (@410) and a control terminal (gate), wherein the first terminal of the first switch is configured to receive an input voltage (VDD); and a second switch (L/S FET) having a first terminal (@410), a second terminal (@GND) and a control terminal (gate), wherein the first terminal of the second switch is coupled to the second terminal of the first switch (@410), and the second terminal of the second switch is configured to be coupled to a reference voltage level (GND).
Regarding Claim 14, Zou discloses (fig. 1-6) a first output pin coupled to the first terminal of the second switch of the first power unit (@410), wherein the first output pin is configured to be coupled to a first inductor (L of 120A); and a second output pin coupled to the first terminal of the second switch of the second power unit, wherein the second output pin is configured to be coupled to a second inductor (L of 120B), wherein an inductance of the first inductor is greater than an inductance of the second inductor (¶21, when 120A Is on and 120B is off).
Regarding Claim 15, Zou discloses (fig. 1-6) the first power unit is turned on to provide a first current to a load via the first output pin when the mode command indicates a light load condition (¶21).
Regarding Claim 16, Zou discloses (fig. 1-6) when the mode command indicates a heavy load condition, the first power unit is turned on provide a first current to a load via the first output pin and the second power unit is turned on to provide a second current to the load via the second output pin (¶42); wherein the sum of the first current and the second current is a phase current for a multiphase voltage regulator (¶19).
Regarding Claim 17, Zou discloses multiphase voltage regulator (fig. 1-6), comprising: a plurality of power stage circuits (120A-120C), each of which is configured to provide a phase current (¶17), wherein each power stage circuit comprises at least one power switch (H/S FET); and a control circuit (110) coupled to the power stage circuits; wherein one of the power stage circuits comprises: a switching control pin configured to receive a control signal (PWM) from the control circuit; a first power unit (120A) having at least one power switch (H/S FET); a second power unit (120B) having at least one power switch (H/S FET); and a driving control circuit (121A) configured to provide at least one first driving signal to the first power unit in response to the control signal, and provide at least one second driving signal to the second power unit in response to the control signal wherein the first power unit is turned on to perform a switching operation and the second power unit is turned off under a first load condition (light load, ¶21, 22), and both the first power unit and the second power unit are turned on to perform a switching operation under a second load condition (normal load, ¶42).
Regarding Claim 18, Zou discloses (fig. 1-6) each of the first power unit and the second power unit comprises: a first switch (HS Fet) having a first terminal (@VDD), a second terminal (@410) and a control terminal (gate), wherein the first terminal of the first switch is configured to receive an input voltage (VDD); and a second switch having a first terminal (@410), a second terminal (@GND) and a control terminal (gate), wherein the first terminal of the second switch is coupled to the second terminal of the first switch (@410), and the second terminal of the second switch is configured to be coupled to a reference voltage level (GND).
Regarding Claim 19, Zou discloses (fig. 1-6) a first output pin coupled to the first terminal of the second switch of the first power unit, wherein the first output pin is configured to provide a first current; and a second output pin coupled to the first terminal of the second switch of the second power unit, wherein the second output pin is configured to provide a second current; wherein the sum of the first current and the second current is the phase current (¶19).
Regarding Claim 20, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit is turned on and the second power unit is turned off when the mode command indicates a light load condition (¶21).
Regarding Claim 21, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit is turned on and the second power unit is turned off when the mode command indicates a discontinuous conduction mode (DCM) operation (¶27).
Regarding Claim 22, Zou discloses (fig. 1-6) a mode pin coupled to the first power unit and the second power unit, wherein the mode pin is configured to receive a mode command (ENABLE); wherein the first power unit and the second power unit are turned on when the mode command indicates a full phase operation (¶42).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20090256535, Houston; Michael J. et al. discloses a varying operation of a voltage regulator, and components thereof, based upon load conditions.
US 20100226149, Masumoto; Hiroshi discloses a power-supply control device and power-supply apparatus therewith
US 20110169476, Ikriannikov; Alexandr et al. discloses an asymmetrical coupled inductors and associated methods.
US 20130027009, Tang; Benjamim et al. discloses a switching regulator with increased light load efficiency.
US 20170248996, Zhang; Kejiu et al. discloses a voltage regulator and method of controlling a voltage regulator comprising a variable inductor.
US 20260121540, Lee; Cheng-Dong et al. discloses a status report of power stage circuit for multiphase voltage regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE J MOODY whose telephone number is (571)272-5242. The examiner can normally be reached on M-F 10 AM - 4 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KYLE J MOODY/
Primary Examiner, Art Unit 2838
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