Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
The response filed 6/22/2026 was received and considered.
Claim Objections
Claims 9-16 are objected to because of the following informalities: In claim 9, line 8, “compelted writing the firmare” should be replaced with “completed writing the firmware”. Claims 10-16 inherit the deficiency. Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6, 8, 17 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Alveo Card Management Solution Subsystem v3.0” by Xilinx.
Regarding claim 1, Xilinx discloses an electronic system, comprising: a controller (CMS subsystem, p. 6, Figure 1), wherein the controller is coupled with a host (server, p. 6, Fig. 1) and configured with first information, the first information indicating that the controller comprises a first memory space accessible to the host (CMS mailbox interface, p. 9, indicates availability to host using CONTROL_REG, p. 10, 1) via a Peripheral Component Interconnect express (PCle) bus (host communicates with CMS subsystem via PCIe, p. 6, Figure 1); and the host, wherein the host is configured to: read the first information from the controller (host checks the availability of the mailbox by confirming CONTROL_REG, p. 10, 1); and responsive to reading the first information, write a firmware image into the first memory space based on the first information without using an NVMe firmware download command (host writes request to mailbox, p. 10, 2, host sets CONTROL_REG to 1 to indicate a new request message is available to CMS, p. 10, 3; firmware update uses mailbox interface to transfer firmware images, p. 11).
Regarding claim 17, the claim is similar in scope to claim 1 and is therefore rejected using a similar rationale.
Regarding claim 2, Xilinx discloses wherein the controller comprises a PCIe interface through which the controller is coupled to the host (CMS subsystem uses PCIe subsystem to communicate with host, p. 6, Figure 1).
Regarding claim 4, Xilinx discloses wherein the controller comprises a memory, and the memory comprises the first memory space (CMS comprises register map and LMB memory, p. 6, Figure 1).
Regarding claims 6 and 19, Xilinx discloses wherein the first memory space (CMS comprises register map and LMB memory, p. 6, Figure 1) comprises a first region and a second region, the host is further configured to write second information into the second region (host sets CONTROL_REG to 1 to indicate a new request message is available to CMS, p. 10, 3) after writing the firmware image into the first region (host writes request to mailbox, p. 10, 2, host sets CONTROL_REG to 1 to indicate a new request message is available to CMS, p. 10, 3; firmware update uses mailbox interface to transfer firmware images, p. 11), and the controller is configured to process the firmware image in the first region responsive to the second information existing in the second region (firmware update uses mailbox interface to transfer firmware images, p. 11; after host sets CONTROL_REG to 1 indicating a new message is available, the host waits for CMS to set CONTROL_REG to 0 indicating a response is in the mailbox, p. 10, 3-4).
Regarding claim 8, Xilinx discloses wherein the electronic system further comprises a memory device coupled with the controller (Satellite controller which firmware controls, p. 8), the firmware image comprises stored data (p. 11, § Satellite Controller Firmware Update), and the controller is configured to write the stored data into the memory device (upgrades satellite controller firmware, p. 11).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 9-10, 12-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xilinx, as applied to claims 6 and 19, in view of US 2022/0091750 A1 (Kang et al.).
Regarding claims 7 and 20, Xilinx lacks wherein the controller comprises a processor configured to: verify the firmware image responsive to the second information existing in the second region; and run the firmware image responsive to the firmware image passing the verification. However, Kang, in an analogous art (firmware verification by a memory controller, abstract), teaches that it was known to download a firmware image from a host (Fig. 1; Fig. 2, S110) and verify the firmware image (Fig. 2, S120), such that the “firmware image verifier 211 may compare a result, generated by the verification algorithm 214, with information stored in the second area of the image buffer 213”, as a means to verify the firmware image integrity (“image buffer 213 may be considered to include a first area configured to store the firmware update information of the firmware image 110 and a second area configured to store the authentication information of the firmware image 110…the authentication information may include signature Sig for firmware image chunks”, ¶66). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Xilinx such that controller comprises a processor configured to: verify the firmware image responsive to the second information existing in the second region; and run the firmware image responsive to the firmware image passing the verification. One of ordinary skill in the art would have been motivated to perform such a modification to enable cryptographic verification of the firmware image, as taught by Kang.
Regarding claim 9, Xilinx discloses a controller (CMS subsystem, p. 6, Figure 1), comprising: a processor (MicroBlaze processor, p. 6, Fig. 1) configured to: configure first information in the controller, the first information indicating that there is a first memory space in the controller for a host to write (CMS mailbox interface, p. 9, indicates availability to host using CONTROL_REG, p. 10, 1) a firmware image (host writes request to mailbox, p. 10, 2, host sets CONTROL_REG to 1 to indicate a new request message is available to CMS, p. 10, 3; firmware update uses mailbox interface to transfer firmware images, p. 11), the first memory space including first and second regions (CMS comprises register map and LMB memory, p. 6, Figure 1); accept a firmware image responsive to second information existing in the second region (host writes firmware to mailbox, p. 10, § Using the Mailbox; host writes request to mailbox, p. 10, 2, host sets CONTROL_REG to 1 to indicate a new request message is available to CMS, p. 10, 3; firmware update uses mailbox interface to transfer firmware images, p. 11), wherein the second information is written by the host into the second region to indicate that the host has completed writing the firmware image into the first region (host writes firmware to mailbox, p. 10, § Using the Mailbox; host writes request to mailbox, p. 10, 2, host sets CONTROL_REG to 1 to indicate a new request message is available to CMS, p. 10, 3; firmware update uses mailbox interface to transfer firmware images, p. 11). Xilinx lacks configuration to verify a firmware image stored in the first region responsive to second information existing in the second region and run the firmware image responsive to the firmware image passing the verification. However, Kang, in an analogous art (firmware verification by a memory controller, abstract), teaches that it was known to download a firmware image from a host (Fig. 1; Fig. 2, S110), verify the firmware image (Fig. 2, S120), such that the “firmware image verifier 211 may compare a result, generated by the verification algorithm 214, with information stored in the second area of the image buffer 213”, as a means to verify the firmware image integrity (“image buffer 213 may be considered to include a first area configured to store the firmware update information of the firmware image 110 and a second area configured to store the authentication information of the firmware image 110…the authentication information may include signature Sig for firmware image chunks”, ¶¶66-67) and run the firmware based on the verification (¶56). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Xilinx such that controller comprises configuration to verify a firmware image stored in the first region responsive to second information existing in the second region and run the firmware image responsive to the firmware image passing the verification. One of ordinary skill in the art would have been motivated to perform such a modification to enable cryptographic verification of the firmware image, as taught by Kang.
Regarding claim 10, Xilinx discloses wherein the controller comprises a PCIe interface through which the controller is coupled to the host (CMS subsystem uses PCIe subsystem to communicate with host, p. 6, Figure 1).
Regarding claim 12, Xilinx discloses wherein the controller comprises a memory, and the memory comprises the first memory space (CMS comprises register map and LMB memory, p. 6, Figure 1).
Regarding claim 13, Xilinx disclose wherein the processor is configured to process the firmware image in the first region responsive to the second information existing in the second region (firmware update uses mailbox interface to transfer firmware images, p. 11; after host sets CONTROL_REG to 1 indicating a new message is available, the host waits for CMS to set CONTROL_REG to 0 indicating a response is in the mailbox, p. 10, 3-4), wherein the second information is to indicate that the host has written the firmware image into the first region (p. 10, 2-3).
Regarding claim 14, Xilinx discloses wherein the electronic system further comprises a memory device coupled with the controller (Satellite controller which firmware controls, p. 8), the firmware image comprises stored data (p. 11, § Satellite Controller Firmware Update), and the controller is configured to write the stored data into the memory device (upgrades satellite controller firmware, p. 11).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Xilinx and Kang, as applied to claim 9, in view of 2021/0311887 A1 to Hieb.
Regarding claim 15, Xilinx discloses wherein the controller further comprises a first firmware (CMS firmware, p. 4, § Introduction) and the processor is configured to run the first firmware to configure the first information in the controller (CMS firmware sets to 0, indicating the CMS response message is in the mailbox, p. 10; thus, by step 1, CMS will have set CONTROL_REG to 0) but lacks a read-only memory device, a first firmware is stored in the read-only memory device. However, Hieb teaches that it was known to utilize a memory controller accessing micro-code (firmware) in a read-only memory (ROM) (¶28), where the micro-code allows the memory sub-system controller to receive the firmware from the host system (¶28). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify Xilinx such that the controller further comprises a read-only memory device, a first firmware is stored in the read-only memory device (boot ROM storing micro-code for current firmware/pre-firmware), and the processor is configured to run the first firmware to configure the first information in the controller (execute micro-code for at least firmware upgrade). One of ordinary skill in the art would have been motivated to perform such a modification to enable the system to contain protected firmware for the CMS, as taught by Hieb.
Regarding claim 16, Xilinx, as modified, teaches wherein the processor is further configured to run the first firmware responsive to the controller being powered on and booted (as modified, Xilinx executes boot ROM, per Hieb ¶28).
Allowable Subject Matter
Claims 3, 5, 11 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3 and 11:
“NVM Express Base Specification (Revision 2.0d)” (NVM Express) teaches wherein the controller comprises a Base Address Register (BAR) (persistent memory region defined by PCI base address register (BAR), where the BAR exposes a region of memory over PCIe, p. 410, §8.14)
US 20230359376 A1 (PINTO; Oscar P. et al.) teaches that it was known for a host controller to communicate with memory devices using NVMe over PCIe (¶93), including implementing a base address register (BAR) to expose memory accessible by the host, including for a controller memory buffer (CMB) (¶93).
However, the prior art – individually, or in a reasonable combination – fails to teach the limitation in the context of the claims as a whole.
Regarding claims 5 and 18:
“NVM Express Base Specification (Revision 2.0d)” (NVM Express) teaches an Identify Controller Data structure to indicate a size of a first memory space (Total NVM Capacity, p. 273).
US 11226755 B1 (Douglass; Christopher J. et al.) teaches that it was known for a controller to indicate a size of memory to expose to a host (interrupt handler selects a base address register (BAR) memory-mapping space, specifies the lowest address of the memory range to expose to the host controller, specifies the highest address of the memory range to expose to the host controller, and enables the BAR and configures the size of the memory range to request in the host's memory map, col. 5, lines 15-22) and to write data into the first memory space based on the first information comprising: assigning an address corresponding to the first memory space based on the size of the first memory space (host directly accesses SPI memory using NVMe, where host memory is mapped to SPI flash, col. 4, lines 1-15); and writing the firmware image into the first memory space based on the address (host access SPI memory based on mapping, co. 4, lines 1-15; host commands can include read and write requests, col. 3 lines 46-49, including writing firmware, col. 6, lines 56-60).
However, However, the prior art – individually, or in a reasonable combination – fails to teach wherein the first information is further to indicate a size of the first memory space, and the host is further configured to: assign an address corresponding to the first memory space based on the size of the first memory space and write the firmware image into the first memory space based on the address, in the context of the claims as a whole.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20050160257 A1 (Kruger, Jack C. et al.) teaches downloading firmware into a storage location and setting a new firmware available flag (Fig. 3).
US 20200073652 A1 (Chen; Jia-Hui) teaches a computer system driver downloading firmware and setting a flag indicating the firmware location, where the system reboots and the bootloader checks the flag to determine whether new firmware exists (¶¶23-31).
US 20230094111 A1 (BENISTY; Shay) teaches an NVMe controller executing firmware (¶30) from read-only memories (¶¶26-27).
US 20220222348 A1 (VASWANI; Kapil et al.) teaches trusted updating of firmware.
US 20250335178 A1 (Rao; Sira Parasurama et al.) teaches a host writing firmware activation instructions to a controller (Fig. 1).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J SIMITOSKI whose telephone number is (571)272-3841. The examiner can normally be reached Monday - Friday, 7:00-3:00.
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/Michael Simitoski/ Primary Examiner, Art Unit 2493
August 19, 2026
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