Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, the limitation “the Base Address Register” lacks sufficient antecedent basis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “NVM Express Base Specification” (Revision 2.0d) (NVMe).
Regarding claim 1, NVMe discloses an electronic system, comprising: a controller (p. 29, Figure 6; see also p. 36, Figure 13 and p. 20, §1.5.14), wherein the controller is coupled with a host (p. 29, Figure 6; see also p. 36, ¶1) and configured with first information (Identify Controller Data Structure, pp. 261-286, §5.17.2), the first information indicating that the controller comprises a first memory space (Firmware Updates (FRMW), including Number Of Firmware Slots (NOFS) and First Firmware Slot Read Only (FFSRO), p. 270); and the host (p. 29, Figure 6; see also p. 36, ¶1), wherein the host is configured to: read the first information from the controller (host uses Identify Controller command, which returns a data buffer including the Identify Controller data structure, p. 258, §5.17; firmware update utilizes Firmware Update Granularity indicated in the Identify Controller data structure, p. 145, ¶1); and responsive to reading the first information, write a firmware image into the first memory space based on the first information (firmware update utilizes Firmware Update Granularity indicated in the Identify Controller data structure, p. 145, ¶1; host submits a Firmware Commit command on that controller with a Commit Action, p. 145, ¶2; the downloaded firmware image should replace the firmware image in the firmware slot, p. 145, ¶2; the Firmware Commit command verifies that a valid firmware image has been downloaded and commits that revision to a specific firmware slot, p. 183, §5.12; Commit Action specifies firmware slot, p. 184, Figure 182).
Regarding claim 2, NVMe discloses wherein the controller comprises a Peripheral Component Interconnect express (PCIe) interface through which the controller is coupled to the host (interface supports PCI Express, p. 14, §1.1, ¶1; p. 14, Figure 1; p. 20, §1.5.14).
Regarding claim 4, NVMe discloses wherein the controller comprises a memory, and the memory comprises the first memory space (host uses Identify Controller command, which returns a data buffer stored in the controller memory including the Identify Controller data structure, p. 258, §5.17; firmware update utilizes Firmware Update Granularity indicated in the Identify Controller data structure, p. 145, ¶1).
Regarding claim 8, NVMe discloses wherein the electronic system further comprises a memory device coupled with the controller (firmware slot, p. 144, §3.11, 2.), the firmware image comprises stored data (firmware image is downloaded, p. 144, §3.11, 1.), and the controller is configured to write the stored data into the memory device (p. 144, §3.11, 1.).
Regarding claim 17, NVMe discloses a method of operating a host (host, p. 29, Figure 6; see also p. 36, ¶1) coupled with a controller (p. 29, Figure 6; see also p. 36, Figure 13 and p. 20, §1.5.14) configured with first information (Identify Controller Data Structure, pp. 261-286, §5.17.2) indicating that there is a first memory space in the controller (Firmware Updates (FRMW), including Number Of Firmware Slots (NOFS) and First Firmware Slot Read Only (FFSRO), p. 270), wherein the method comprises: reading the first information from the controller (host uses Identify Controller command, which returns a data buffer including the Identify Controller data structure, p. 258, §5.17; firmware update utilizes Firmware Update Granularity indicated in the Identify Controller data structure, p. 145, ¶1); and writing a firmware image into the first memory space based on the first information (firmware update utilizes Firmware Update Granularity indicated in the Identify Controller data structure, p. 145, ¶1; host submits a Firmware Commit command on that controller with a Commit Action, p. 145, ¶2; the downloaded firmware image should replace the firmware image in the firmware slot, p. 145, ¶2; the Firmware Commit command verifies that a valid firmware image has been downloaded and commits that revision to a specific firmware slot, p. 183, §5.12; Commit Action specifies firmware slot, p. 184, Figure 182).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over NVMe, as applied to claim 2, in view of in view of US 2023/0359376 A1 (Pinto et al.).
Regarding claim 3, NVMe discloses wherein the controller comprises a Base Address Register (BAR) (persistent memory region defined by PCI base address register (BAR), where the BAR exposes a region of memory over PCIe, p. 410, §8.14), but lacks that the first information is configured in the BAR, and the first information comprises a value of the BAR. However, Pinto teaches that it was known for a host controller to communicate with memory devices using NVMe over PCIe (¶93), including implementing a base address register (BAR) to expose memory accessible by the host, including for a controller memory buffer (CMB) (¶93). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify NVMe such that the first information is configured in the BAR (base address configured to expose the controller memory to the host), and the first information comprises a value of the BAR (base address configured to expose the controller memory to the host). One of ordinary skill in the art would have been motivated to perform such a modification to transfer the image between a host the controller, using PCIe and NVMe, as taught by Pinto.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over NVMe, as applied to claim 1 and 17, in view of in view of US 11,226,755 B1 (Douglass et al.).
Regarding claims 5 and 18, wherein the first information (Identify Controller Data structure) is further to indicate a size of the first memory space (Total NVM Capacity, p. 273), but lacks where writing the firmware image into the first memory space based on the first information comprises: assigning an address corresponding to the first memory space based on the size of the first memory space; and writing the firmware image into the first memory space based on the address. However, Douglass teaches that it was known for a controller to indicate a size of memory to expose to a host (interrupt handler selects a base address register (BAR) memory-mapping space, specifies the lowest address of the memory range to expose to the host controller, specifies the highest address of the memory range to expose to the host controller, and enables the BAR and configures the size of the memory range to request in the host's memory map, col. 5, lines 15-22) and to write data into the first memory space based on the first information comprising: assigning an address corresponding to the first memory space based on the size of the first memory space (host directly accesses SPI memory using NVMe, where host memory is mapped to SPI flash, col. 4, lines 1-15); and writing the firmware image into the first memory space based on the address (host access SPI memory based on mapping, co. 4, lines 1-15; host commands can include read and write requests, col. 3 lines 46-49, including writing firmware, col. 6, lines 56-60). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify NVMe such that the first information is further to indicate a size of the first memory space, and writing the firmware image into the first memory space based on the first information comprises: assigning an address corresponding to the first memory space based on the size of the first memory space; and writing the firmware image into the first memory space based on the address. One of ordinary skill in the art would have been motivated to perform such a modification to establish a mapping between host memory and the controller memory, to enable downloading of data, including the firmware image, to the controller memory using PCIe, as taught by Douglass.
Claims 6-7, 9-10, 12-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over “NVM Express Base Specification” (Revision 2.0d) (NVMe), in view of US 2022/0091750 A1 (Kang et al.).
Regarding claim 6, NVMe discloses that the controller may employ second information (additional vendor specific means (e.g., checksum, CRC, cryptographic hash, or a digital signature) to determine the validity of a firmware image) (p. 144, §3.11), but lacks wherein the first memory space comprises a first region and a second region, the host is further configured to write second information into the second region after writing the firmware image into the first region, and the controller is configured to process the firmware image in the first region responsive to the second information existing in the second region. However, Kang, in an analogous art (firmware verification by a memory controller, abstract), teaches that it was known to download a firmware image from a host (Fig. 1; Fig. 2, S110) and verify the firmware image (Fig. 2, S120), such that the “firmware image verifier 211 may compare a result, generated by the verification algorithm 214, with information stored in the second area of the image buffer 213”, as a means to verify the firmware image integrity (“image buffer 213 may be considered to include a first area configured to store the firmware update information of the firmware image 110 and a second area configured to store the authentication information of the firmware image 110…the authentication information may include signature Sig for firmware image chunks”, ¶66). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify NVMe such that the first memory space comprises a first region and a second region (for storing a firmware image and authentication information), the host is further configured to write second information into the second region after writing the firmware image into the first region (writing the firmware and signature), and the controller is configured to process the firmware image in the first region responsive to the second information existing in the second region (verify the firmware image according to the signature). One of ordinary skill in the art would have been motivated to perform such a modification to enable cryptographic verification of the firmware image, as taught by Kang.
Regarding claim 7, NVMe, as modified, teaches wherein the controller comprises a processor configured to: verify the firmware image responsive to the second information (controller may employ second information (additional vendor specific means (e.g., checksum, CRC, cryptographic hash, or a digital signature)) to determine the validity of a firmware image, NVMe, p. 144, §3.11) existing in the second region (as modified by Kang); and run the firmware image responsive to the firmware image passing the verification (Firmware Commit command verifies that the last firmware image downloaded is valid based on validity checks, including signature, and commits that firmware image to the firmware slot; host performs a reset, controller is re-initialized, NVMe, p. 144, §3.11).
Regarding claim 9, NVMe discloses a controller (p. 29, Figure 6; see also p. 36, Figure 13 and p. 20, §1.5.14), comprising: a processor (controller is the interface between a host and an NVM subsystem and executes commands submitted by a host on a Submission Queue and posts a completion on a Completion Queue, p. 20, §1.5.14) configured to: configure first information (controller maintains Identify Controller data structure, p. 258, §5.17; see also Identify Controller Data Structure, pp. 261-286, §5.17.2) in the controller, the first information indicating that there is a first memory space in the controller (Identify Controller data structure includes Firmware Updates (FRMW), including Number Of Firmware Slots (NOFS) and First Firmware Slot Read Only (FFSRO), p. 270; Identify Controller data structure identifies additional memory space - Controller Attributes (CTRATT) (attributes of the controller), including Extended LBA Formats Supported (ELBAS), p. 264, Total NVM Capacity (TNVMCAP) (p. 273) and Unallocated NVM Capacity (UNVMCAP), p. 273), the first memory space including first and second regions (at least firmware slots; Number Of Firmware Slots (NOFS): This field indicates the number of firmware slots supported by the domain that contains this controller. This field shall specify a value from one to seven, indicating that at least one firmware slot is supported and up to seven maximum. This corresponds to firmware slots 1 through 7, p. 270); verify a firmware image stored in the first region (controller may employ additional vendor specific means (e.g., checksum, CRC, cryptographic hash, or a digital signature) to determine the validity of a firmware image, p. 144, §3.11); and run the firmware image responsive to the firmware image passing the verification (Firmware Commit command verifies that the last firmware image downloaded is valid based on validity checks, including signature, and commits that firmware image to the firmware slot; host performs a reset, controller is re-initialized, p. 144, §3.11). NVMe discloses that the controller may employ second information (additional vendor specific means (e.g., checksum, CRC, cryptographic hash, or a digital signature) to determine the validity of a firmware image) (p. 144, §3.11), but lacks responsive to second information existing in the second region. However, Kang, in an analogous art (firmware verification by a memory controller, abstract), teaches that it was known to download a firmware image from a host (Fig. 1; Fig. 2, S110) and verify the firmware image (Fig. 2, S120), such that the “firmware image verifier 211 may compare a result, generated by the verification algorithm 214, with information stored in the second area of the image buffer 213”, as a means to verify the firmware image integrity (“image buffer 213 may be considered to include a first area configured to store the firmware update information of the firmware image 110 and a second area configured to store the authentication information of the firmware image 110…the authentication information may include signature Sig for firmware image chunks”, ¶66). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify NVMe such that the firmware image verification (using checksum, CRC, cryptographic hash, or a digital signature), is performed responsive to second information existing in the second region (authentication information of the firmware image 110; signature Sig for firmware image chunks). One of ordinary skill in the art would have been motivated to perform such a modification to enable cryptographic verification of the firmware image, as taught by Kang.
Regarding claim 10, NVMe discloses wherein the controller comprises a Peripheral Component Interconnect express (PCIe) interface through which the controller is coupled to the host (interface supports PCI Express, p. 14, §1.1, ¶1; p. 14, Figure 1; p. 20, §1.5.14).
Regarding claim 12, NVMe discloses wherein the controller comprises a memory, and the memory comprises the first memory space (host uses Identify Controller command, which returns a data buffer stored in the controller memory including the Identify Controller data structure, p. 258, §5.17; firmware update utilizes Firmware Update Granularity indicated in the Identify Controller data structure, p. 145, ¶1).
Regarding claim 13, NVMe, as modified, teaches wherein the processor is further configured to process the firmware image in the first region responsive to the second information existing in the second region (Kang, storing authentication information in second region, Kang, ¶66), wherein the second information is to indicate that a host has written the firmware image into the first region (storing authentication information of the firmware image 110; signature Sig for firmware image chunks, Kang, ¶66).
Regarding claim 14, NVMe discloses wherein the controller is coupled with a memory device (firmware slot, p. 144, §3.11, 2.), the firmware image comprises stored data (firmware image is downloaded, p. 144, §3.11, 1.), and the controller is configured to write the stored data into the memory device (p. 144, §3.11, 1.).
Regarding claim 19, NVMe, as modified, teaches wherein the first memory space comprises a first region and a second region (Kang, ¶66; Fig. 6), and the method further comprises: writing second information into the second region after writing the firmware image into the first region (Kang, storing authentication information in second region, Kang, ¶66), wherein the second information is to indicate that the host has written the firmware image into the first region (storing authentication information of the firmware image 110; signature Sig for firmware image chunks, Kang, ¶66).
Regarding claim 20, NVMe, as modified, teaches wherein the second information into the second region causes the controller to: verify the firmware image responsive to the second information (controller may employ second information (additional vendor specific means (e.g., checksum, CRC, cryptographic hash, or a digital signature)) to determine the validity of a firmware image, NVMe, p. 144, §3.11) existing in the second region (as modified by Kang); and run the firmware image responsive to the firmware image passing the verification (Firmware Commit command verifies that the last firmware image downloaded is valid based on validity checks, including signature, and commits that firmware image to the firmware slot; host performs a reset, controller is re-initialized, NVMe, p. 144, §3.11).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over NVMe and Kang, as applied to claim 10, in view of Pinto.
Regarding claim 11, NVMe, as modified, discloses wherein the controller comprises a Base Address Register (BAR) (persistent memory region defined by PCI base address register (BAR), where the BAR exposes a region of memory over PCIe, p. 410, §8.14), but lacks that the first information is configured in the BAR. However, Pinto teaches that it was known for a host controller to communicate with memory devices using NVMe over PCIe (¶93), including implementing a base address register (BAR) to expose memory accessible by the host, including for a controller memory buffer (CMB) (¶93). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify NVMe such that the first information is configured in the BAR (base address configured to expose the controller memory to the host). One of ordinary skill in the art would have been motivated to perform such a modification to transfer the image between a host the controller, using PCIe and NVMe, as taught by Pinto.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over NVMe and Kang, as applied to claim 9, in view of 2021/0311887 A1 to Hieb.
Regarding claim 15, NVMe discloses wherein the controller further comprises a read-only firmware (read-only firmware image, p. 145, second to last paragraph), but lacks a read only memory device, where the first firmware is stored in the read-only memory device, and the processor is configured to run the first firmware to configure the first information in the controller. However, Hieb teaches that it was known to utilize a memory controller accessing micro-code (firmware) in a read-only memory (ROM) (¶28), where the micro-code allows the memory sub-system controller to request the firmware from the host system (¶28). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further modify NVMe such that the controller further comprises a read-only memory device, a first firmware is stored in the read-only memory device (micro-code for current firmware/pre-firmware), and the processor is configured to run the first firmware to configure the first information in the controller (execute micro-code for at least firmware upgrade). One of ordinary skill in the art would have been motivated to perform such a modification to enable the system to contain protected firmware for accessing firmware updates, as taught by Hieb.
Regarding claim 16, NVMe, as modified, teaches wherein the processor is further configured to run the first firmware responsive to the controller being powered on and booted (system must be powered on to operate; micro-code is boot-ROM, where code is executed for booting device following power on, ¶28).
Conclusion
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/Michael Simitoski/ Primary Examiner, Art Unit 2493
March 18, 2026
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