DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/20/2024 has been considered and placed on record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2015/0372803 A1, hereinafter, “Jiang”) in views of Riani et al. (US 9,258,155 B1, hereinafter, “Riani”) and Dallaire et al. (US 9,559,877 B1, hereinafter, “Dallaire”).
Consider claim 10, Jiang teaches an apparatus (see at least figures 1, 8, 9 and description thereof), comprising: processing circuitry associated with one or more memory devices (see at least figure 9) and configured to cause the apparatus to: receive a signal having inter-symbol interference (see at least figure 1, 8 and 9 and para. 2, Jiang teaches receiving data signal which inherently includes inter-symbol interference (ISI)), wherein the signal has been modulated using a modulation scheme that includes two or more voltage levels (see at least figure 8 and para. 56, Jiang teaches modulating signal using a modulation scheme that includes two or more voltage levels (2-PAM)); reduce, using a receiver circuit, the inter-symbol interference of clock signal phase of the signal (see at least paras. 2 and 56, Jiang teaches reducing ISI of clock signal phase); and adaptive loop filter suppressing excess ISI (figure 8, paras. 56-58).
Jiang teaches wherein the signal has been modulated using a modulation scheme that includes two or more voltage levels (see above), however, did not particularly teach the signal has been modulated using a modulation scheme that includes three or more voltage levels. Riani teaches said technique (see at least col. 2 lines 16-26, col. 8 line 34- col. 9 line 5, where Riani teaches signal being modulated in 4-PAM levels).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Jiang and teach the signal has been modulated using a modulation scheme that includes three or more voltage levels, as taught by Riani, thereby having efficient transmission technique.
Jiang teaches reduce, using a receiver circuit, the inter-symbol interference of clock signal phase of the signal (see above), however, did not particularly teach the inter-symbol interference of between a plurality of clock signal phases of a signal. Dallaire teaches (see at least abstract, where Dallaire teaches clock phases of a signal having ISI, thus ISI between clock phases).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Jiang and teach the inter-symbol interference of between a plurality of clock signal phases of a signal, as taught by Dallaire, thereby having efficient transmission technique.
Jiang teaches adaptive loop filter suppressing excess ISI (figure 8, paras. 56-58), however, did not particularly teach decode one or more symbols of the signal based at least in part on reducing the inter-symbol interference. Riani teaches (see at least figure (508), col. 10 lines 30-47 and 56-64, Riani teaches decode symbols after the reduction of ISI, thus decode the symbols based on the reduced ISI).
It would have been obvious to one of ordinary skill in the art at the time of the application to modify the invention of Jiang and teach decode one or more symbols of the signal based at least in part on reducing the inter-symbol interference, as taught by Riani, thereby having efficient transmission technique.
Consider claim 1, all the limitations of method claim 1 are included in the apparatus claim 10, therefore, claim 1 is subjected to the same rejection.
Consider claim 17, all the limitations of non-transitory computer-readable medium (see at least para. 71), are included in the apparatus claim 10, therefore, claim 17 is subjected to the same rejection.
Allowable Subject Matter
Claims 2-9, 11-16 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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FITWI Y. HAILEGIORGIS
Primary Examiner
Art Unit 2632
/FITWI Y HAILEGIORGIS/ Examiner, Art Unit 2632
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