Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of new grounds of rejection.
Claim Rejections - 35 USC § 103
Claim(s) 1-3, 5-10,12-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Uminski (US 20210006511 A1) in view of Louzoun (US 20200228467 A1) and in further view of Labonte (US 20170005951 A1).
As for Claims 1, 8 and 15 Uminski discloses A network interface controller (NIC 101 – fig.1), comprising:
first resources (i.e. (PF 0, RDMA QP 106, LAN RXQ 108, VSI 114 and port 122 – fig.1a) configured to supply first traffic (i.e. LAN or RDMA traffic.) (¶0032 & 0035);
second resources (i.e. PF 1, LAN RXQ 110, VSI 116, and port 124 – fig.1a) configured to supply second traffic (i.e. backup/ control traffic) (¶0032 & 0035).
Uminski does not disclose a load balancer, coupled to the first and second resources configured to balance the first traffic and the second traffic between first and second port circuits of a link aggregation group (LAG) using a hash function; and remote direct memory access (RDMA) logic configured to, using the hash function, divide work requests into a first set of work requests for first packets that hash to the first port circuit and a second set of work requests for second packets that hash to the second port circuit, the RDMA logic configured to supply the first set of work requests to the first resources and the second set of work requests to the second resources.
In an analogous art, Louzoun discloses a load balancer coupled to the first and second resources (i.e. PF driver 320 can load balance use of ports 354-0 and 354 by associating host schedulers with port schedulers . PF driver can tie a tx queue of a VEE to a host scheduler )( ¶0039 & 0053) configured to balance the first traffic and the second traffic between first and second port circuits of a link aggregation group using a hash function (i.e. a PF driver 320 can apply an equal weighting scheme (e.g., hash) to select a port for transmission for a packet) (¶ 0044 & 0052) and
remote direct memory access (RDMA) logic configured to, using the hash function, divide work requests (i.e., Host scheduler node can decide which Tx queue to schedule to a port for transmission based on bandwidth available at a port. ) into a first set of work requests for first packets that hash to the first port circuit (i.e., distributing the traffic from the different CPUs (or cores) to different ports evenly (e.g., using a hash calculation) can provide load balancing of port usage) and a second set of work requests for second packets that hash to the second port circuit (i.e., PF driver 214 can allocate physical ports to a Switch ID and cause an update of table 254. Tying or association of one or more ports to a Switch ID can occur to provide traffic load balancing among ports or receive (Rx) queues (e.g., hashing across all receive queues to evenly balance received traffic across receive (Rx) queues; ¶0039), the RDMA logic configured to supply the first set of work requests to the first resources and the second set of work requests to the second resources (PF driver 214 can program the switch tables partially or in totality and can program rules to direct packet traffic to an Rx queue. Queues are resources. PF driver 320 can migrate Tx queues among scheduler nodes to manage packet transmit load on one or more ports.)( ¶ 0039, 0053, & 0061).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Uminski to include a load balancer, coupled to the first and second resources, configured to balance the first traffic and the second traffic between first and second port circuits of a link aggregation group (LAG) using a hash function; and remote direct memory access (RDMA) logic configured to, using the hash function, divide work requests into a first set of work requests for first packets that hash to the first port circuit and a second set of work requests for second packets that hash to the second port circuit, the RDMA logic configured to supply the first set of work requests to the first resources and the second set of work requests to the second resources as taught in Louzoun for the benefit of distributing the work requests across multiple transmission resources of a NIC thereby improving throughput efficiency and reducing bottlenecking.
Uminski in view of Louzoun fails to disclose where a first buffer of
the first resources is configured to store the first packets and none of the second packets and a second buffer of the second resources is configured to store the second packets and none of the first packets.
In an analogous art, Labonte discloses,
where a first buffer of the first resources is configured to store the first packets and none of the second packets(i.e. First virtual output queue is associated with a first egress port. Network data destined for the first egress port is buffered in its corresponding VOQ. )(¶0080)and a second buffer of the second resources is configured to store the second packets and none of the first packets(i.e. when ports 416C and 416D have data destined for port 416E, the data from each port is buffered in a separate, dedicated VOQ for that respective input port. A second virtual output queue that is associated with a second egress port. Network data destined for the second egress port is buffered in its corresponding VOQ. By buffering packets in separate VOQ’s the invention may prevent HOL blocking. )(¶0020, 0059 and 0080)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to modify Uminski in view of Louzoun to include
where a first buffer of the first resources is configured to store the first packets and none of the second packets and a second buffer of the second resources is configured to store the second packets and none of the first packets as taught by Labonte for the benefit of preventing HOL blocking.
As for Claims 2 and 12 Uminski in view of Louzoun and Labonte further discloses, in particular Uminski teaches
a bus interface (i.e. I/O interface 623 – fig.6) having a first physical function and a second physical function (i.e., i/o interface provides communication between host and NIC. NIC includes multiple physical functions that are accessible through this interface.) (¶0057 & 0059).
Uminski in view of Louzoun and Labonte discloses, in particular Louzoun teaches,
wherein the RDMA logic, in response to first RDMA work received via the first physical function (i.e., tying a Tx queue to a host scheduler and tying a host scheduler to a port scheduler associated with a transmit (egress) port; ¶ 0053), is configured to add a portion of the first set of work requests for a portion of the first packets to a first group and add a portion of the second set of work requests for a portion of the second packets to a second group (i.e. Host schedulers 312-0, 312-1, 314-0, and 314-1 can select packets for transmission from transmit (TX) queues 306-0 to 306-6 and control packet queues 310-0 to 310-1. packets being directed to queues associated with PF’s, based on port/ port group mapping. Packets being directed to queues associated with PF’s, based on port/ port group mapping)( ¶ 0051, 0053, & 0107);
wherein the RDMA logic, in response to second RDMA work received via the second physical function (i.e. multiple PF drivers are used, where a port has an associated PF driver whereby PF #0 can manage port 354-0 whereas PF driver #1 manage port 354-1. A virtualized execution environment that provides packets to the transmit queue and assign a received packet to a destination queue based at least in part on a port group identifier, wherein the port group identifier is associated with one or more ports.)(¶ 0057, 0059, 0109) is configured to add another portion of the first set of work requests for another portion of the first packets to a third group and add another portion of the second set of work requests for another portion of the second packets to a fourth group. (i.e., hashing across all receive queues to evenly balance received traffic across receive queues. Receive queues correspond to groups and the use of all receive queues indicates scalability beyond a fixed number of groups. Schedulers 312-0 and 312-1 and control packet queue 310-0 provide available packets to scheduler 314-0. Scheduler 312-0 selects available packets from Tx queues 306-0 and 306-1 whereas scheduler 312-1 selects available packets from Tx queues 306-2 and 306-3. Tx queues 306-4 to 306-6 and control packet queue 310-1 provide available packets to scheduler 314-1. Accordingly, the further division into “third group” and “fourth group” corresponds to additional queue/scheduler groupings, which may depend on the PF, the port, the queue, and the work request/packet type, as described in the scheduling and queue allocation logic.) (¶ 0039, 0051, & 0055)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Uminski to include wherein the RDMA logic, in response to first RDMA work received via the first physical function, is configured to add a portion of the first set of work requests for a portion of the first packets to a first group and add a portion of the second set of work requests for a portion of the second packets to a second group as taught by Louzoun for the benefit of grouping work requests by physical function.
As for Claims 3, 10, and 17, Uminski in view Louzoun and Labonte further disclose, in particular Louzoun teaches,
wherein the first and third groups are configured to input to the first resources, and wherein the second and fourth groups are configured to input to the second resources (i.e., hashing across all receive queues to evenly balance received traffic across receive queues. Schedulers 312-0 and 312-1 and control packet queue 310-0 provide available packets Sto scheduler 314-0. Scheduler 312-0 selects available packets from Tx queues 306-0 and 306-1 whereas scheduler 312-1 selects available packets from Tx queues 306-2 and 306-3. Tx queues 306-4 to 306-6 and control packet queue 310-1 provide available packets to scheduler 314-1. Accordingly, the further division into “third group” and “fourth group” corresponds to additional queue/scheduler groupings, which may depend on the PF, the port, the queue, and the work request/packet type, as described in the scheduling and queue allocation logic.) (¶ 0039, 0051, & 0055).
The motivation to combine is similar to that of claim 1.
As for Claims 5, 12, and 19, Uminski in view of Louzoun and Labonte further disclose, in particular Louzoun teaches,
wherein the RDMA logic includes a hash calculator configured to use the hash function to divide the work requests (i.e. distributing the traffic from the different CPUs (or cores) to different ports evenly (e.g., using a hash calculation) can provide load balancing of port usage )( ¶ 0050)
The motivation to combine is similar to that of claim 1.
As for Claims 6, 13, and 20, Uminski in view of Louzoun and Labonte further disclose, in particular Louzoun teaches,
wherein the hash calculator comprises firmware executed by a central processing unit (CPU). (Processor 710 – fig.7)
The motivation to combine is similar to that of claim 1.
As for Claims 7 and 14, Uminski in view of Louzoun and Labonte further disclose, in particular Louzoun teaches,
wherein the hash calculator is configured to obtain a table from the load balancer and divide the work requests into the first set of work requests for the first packets that hash to the first port, and the second set of work requests for the second packets that hash to the second port, using results of the hash function as applied to the table.(i.e. PF driver 214 can allocate physical ports to a Switch ID and cause an update of table 254. Tying or association of one or more ports to a Switch ID can occur to provide traffic load balancing among ports or receive (Rx) queues (e.g., hashing across all receive queues to evenly balance received traffic across receive (Rx) queues). PF driver 214 can program the switch tables partially or in totality and can program rules to direct packet traffic to an Rx queue. PF driver 320 can load balance use of ports 354-0 and 354-1 by associating a tier or arrangement of host schedulers with port schedulers 352-0 and 352-1.) (¶ 0039 and 0052-0053)
The motivation to combine the prior art is similar to that of claim 1.
4. Claims 4, 11 and 18 are rejected under 35 U.S.C. 103(a) as being unpatentable over Uminski (US 20210006511 A1) in view of Louzoun (US 20200228467 A1) and Labonte (US 20170005951 A1) and in further view of Yu (US 20230236756 A1).
As for Claims 4, 11 and 18, Uminski in view of Louzoun and Labonte fails to disclose wherein the first set of resources include a first queue configured to receive the first set of work requests and a first buffer configured to assemble the first packets based on the first set of work requests, and wherein the second resources include a second queue configured to receive the second set of work requests and a second buffer configured to assume the second packets based on the second set of work requests.
In an analogous art, Yu teaches wherein the first set of resources include a first queue (QCB)(i.e. a QCB can be utilized to construct a queue as a linked list of FCB’s)( ¶ 0032) configured to receive the first set of work requests and a first buffer (i.e. buffer memory 112 - fig.1; ¶ 0023) configured to assemble the first packets based on the first set of work requests and wherein the second resources include a second queue configured to receive the second set of work requests and a second buffer configured to assume the second packets based on the second set of work requests.(i.e. buffer manager 110 allocates frame control blocks (FCBs) and associates them with buffer control blocks(BCBs). The buffer manager allocates buffer memory for frames and associates frames with queue structures via FCBs. This enables additional queues to be created via additional QCB instances, with corresponding frames stored in buffer memory 112, thereby disclosing first and second queues and corresponding buffers. Essentially assigning one buffer for every queue) (¶ 0021,0024,0031-0033)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Uminski in view of Louzoun and Labonte to include wherein the first set of resources include a first queue configured to receive the first set of work requests and a first buffer configured to assemble the first packets based on the first set of work requests, and wherein the second resources include a second queue configured to receive the second set of work requests and a second buffer configured to assume the second packets based on the second set of work requests as taught in Yu for the benefit of enabling independent processing of work requests across multiple resources to improve throughput and reduce bottlenecking.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN ESTRADA whose telephone number is (571) 272-9978. The examiner can normally be reached on Monday through Friday, 8:00 AM EST to 4:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRIS PARRY can be reached on (571) 272-8328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JONATHAN ESTRADA/Examiner, Art Unit 2451
/Chris Parry/Supervisory Patent Examiner, Art Unit 2451
