Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 12, 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Farjadrad (US12058874).
As to claim 1, Farjadrad discloses an apparatus (Fig. 1) comprising: a die comprising: a memory interface (Fig. 1, and element 122) ; a die-to-die (D2D) circuit comprising a D2D interface (Fig. 1 and element 118) ; and an intermediate section configured to transfer data using the memory interface and the D2D interface, wherein the intermediate section comprises a transaction converter (Fig. 1, and element 128, COL. 4, lines 22 – 35).
As to claim 2, Farjadrad discloses the apparatus, wherein the intermediate section comprises a memory controller (Fig. 1, and element 126, COL. 4, lines 35 – 40).
As to claim 3, Farjadrad discloses the apparatus, wherein the intermediate section comprises one or more compute resources (Fig. 1, and element 128 executing conversion, COL. 4, lines 44 – 47).
As to claim 4, Farjadrad discloses the apparatus (wherein the intermediate section is configured to transfer data using a protocol (Fig. 1, and COL. 4, lines 55 – 67).
As to claim 5, Farjadrad discloses the apparatus, wherein the D2D interface is configured to transfer data using flow control (Fig. 1, and COL. 4, lines 40 – 45).
As to claim 6, Farjadrad discloses the apparatus, wherein: the D2D interface comprises a D2D link interface (Fig. 1, and link 118 to 120); and the transaction converter is configured to convert a memory transaction to the D2D link interface (Fig. 1, COL. 4, lines 45 – 50).
As to claim 7, Farjadrad discloses the apparatus, wherein the D2D interface is configured to transfer data using a raw format (Fig. 1, COL. 4, lines 45 – 50).
As to claim 8, Farjadrad discloses the apparatus, wherein: the D2D interface comprises a D2D phy interface (Fig. 3 with HBM PHY) ; and the transaction converter is configured to convert a memory transaction to the D2D phy interface (Fig. 3, and COL. 5, lines 20 – 30).
As to claim 9, Farjadrad discloses the apparatus, wherein the intermediate section is configured to pack data into a raw format (Fig. 1, COL. 4, lines 45 – 50).
As to claim 10, Farjadrad discloses the apparatus wherein the D2D interface comprises a D2D link interface (Fig. 1, and element 118) , and the intermediate section (Fig. 1, and element 106) comprises: a memory controller configured to access a memory device using the memory interface Fig. 1, and element 126, COL. 4, lines 35 – 40); and a transaction converter connected to the memory controller using a protocol interface, wherein the transaction converter is configured to convert a memory transaction between the protocol interface and the D2D link interface (Fig. 1, and conversion circuitry 128).
As to claim 11, Farjadrad discloses the apparatus wherein: the D2D interface comprises a D2D link interface (Fig. 1, and element 118); and the intermediate section comprises a transaction converter configured to convert a memory transaction between the memory interface and the D2D link interface (Fig. 1, COL. 4, lines 45 – 50).
As to claim 12, Farjadrad discloses the apparatus wherein: the D2D interface comprises a D2D phy interface (Fig. 3, with element HBM comprising PHY); and the intermediate section comprises a transaction converter configured to convert a memory transaction between the memory interface and the D2D phy interface ((Fig. 3, and COL. 5, lines 20 – 30).
As to claim 16, Farjadrad discloses an apparatus comprising: a die (Fig. 1) comprising: a memory interface (Fig. and element 126); a die-to-die (D2D) circuit comprising a D2D interface (Fig. 1, and element 118); and a transaction converter connected between the memory interface and the D2D interface (Fig. 1, and element 128).
As to claim 17, Farjadrad discloses the apparatus, further comprising a protocol layer connected between the memory interface and the D2D interface (Fig. 3, and COL. 5, lines 20 – 33).
As to claim 18, Farjadrad discloses the apparatus, wherein the D2D circuit comprises a link layer configured to transfer data using flow control (Fig. 3, and COL. 5, lines 34 – 45, where the chosen protocol governs the flow control traffic).
As to claim 19, Farjadrad discloses the apparatus, wherein the D2D circuit comprises a phy layer configured to transfer data using a raw format (Fig. 3, and where each HBM comprises said, COL. 5, lines 20 – 33).
As to claim 20, Farjadrad discloses a method comprising: performing, at a die (Fig. 1, and 100), using a memory interface (Fig. 1, and element 126), a memory transaction (Col. 4, lines 35 – 40); converting, at the die, the memory transaction to a form for a die-to-die (D2D) interface (Col. 4, lines 40 – 50); and transferring, using the D2D interface, data associated with the memory transaction (COL. 3, lines 7 – 15).
Allowable Subject Matter
Claims 13- 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20220342841, US20220222194, and US12204759 teach the interfacing of memory modules and host devices in a D2D module system.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184