Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 20130083615 (CHOI) in view of US20080151647 (MILLER et al).
With respect to claim 1, CHOI teaches DRAM (Dynamic Random Access Memory) including a plurality of mats composed of cell arrays (dynamic random access memory device including a first array of memory cells arranged in rows and columns a second array of memory cells arranged in rows and columns) [Fig. 3A & 3B; Par. 0053] comprising:
a first mat including a first cell array that is aligned by first bitlines and first wordlines
(first array of memory cells arranged in rows and columns arranged at intersection by bitline and wordlines) [Fig. 3A&3B; Par. 0053];
a second mat including a second cell array that is adjacent to the first mat and aligned by second bitlines and second wordlines
(second array of memory cells arranged in rows and columns and arranged at intersection of wordlines 110 and bitlines 112) [Fig. 3A&3B; Par. 0053]; and
a bitline sense amplifier shared by the first bitlines of the first mat and the second bitlines of the second mat
(sense amplifiers 118 disposed between the pairs of arrays, the sense amplifier being adjacent to a bitline concurrently connected) [Fig. 3A&3B; Par. 0053; Par. 0020].
20130083615 CHOI) fails to specifically teach the DRAM memory wherein the bitline sense amplifier connected to the first mat is shared only with the second mat. However, CHOI specifically teaches the sense amplifiers selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least complementary bitline of the second plurality of bitlines (the bitlines 112 coupled to two pairs of sense amplifiers 118 are interleaved, such that (as best seen in FIG. 5) bitlines 112A, 112C, 112E are coupled to one pair of sense amplifiers 118, and bitlines 112B, 112D, 112F are coupled to another pair of sense amplifiers 118) [Abstract; Fig. 5; Par. 0054; Par. 0020-0021]. Nevertheless, MILLER teaches a semiconductor memory device, such as a dynamic random access memory (DRAM) device, a sense amplifier provided where typically in DRAM, the sense amplifier is shared by first and second memory array segments to sense voltage on bitlines to either one memory array segment or the other memory array segment, but never sensing from both memory array segments at the same time [Par. 0002-0003; Par. 0020-0022]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing of the instant application to feature, within CHOI’s dynamic RAM, the bitline sense amplifier connected to the first mat is shared only with the second mat, taught by MILLER, in order to provide the connection feature of the sense node pair of the sense amplifier to and disconnects the sense node pair from, the first memory array, as taught by MILLER [Par. 0003].
With respect to claim 2, CHOI and MILLER, combined teach the DRAM, wherein the bitline sense amplifier includes a first input terminal that is connected to one of the first bitlines and a second input terminal that is connected to one of the second bitlines corresponding to the first bitline connected to the first input terminal (each bitline selectively connects an active wordline at a memory cell is connected to a sense amplifier connected to a bit select line as input) [CHOI’s Fig. 5; Fig. 11; Par.0065].
With respect to claim 10, CHOI and MILLER, combined teach the DRAM, wherein the second cell array stores opposite data or independent data of the first cell array (DRAM device having multiple arrays, each having DRAM cells arranged between wordlines and bitlines with sense amplifiers disposed between pairs of arrays and coupled to the bitlines via corresponding voltage input line) [CHOI’s Par. 0064-0065].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 20130083615 (CHOI) in view of US20080151647 (MILLER et al) and further in view of US 20200334119 A1 (LIM).
With respect to claim 3, CHOI and MILLER, combined teach the invention as claimed, but fails to specifically teach a mode register that selects one of a basic mode, a low-latency mode, or a low-power mode based on memory usage of a server to which the DRAM belongs and an application operating method. However, LIM teaches plurality of memory devices arranged in groups, a system controller configured to control data input/output for each processing group include a power management device configured to configure (activate each group) at least one memory group of the plurality of memory devices based on predetermined power mode (based on an operating voltage characteristic) wherein the predetermined power modes include normal power mode, high speed with low latency mode in response to a request; and power saving mode being an inactive mode [Abstract; Par. 0057-0061; Par. 0079-0080]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing of the instant application to feature, within CHOI’s dynamic RAM, the bitline sense amplifier connected to the first mat is shared only with the second mat, taught by MILLER, and further identify memory usage and an application operation method selecting one of a basic mode, a low-latency mode, or a low-power mode based on the memory usage and the application operating method, as taught by LIM, in order to provide specific memory device with operation at regulated and defined voltage or speed that would improve information processing performance; as taught by LIM [Par. 0079-0080]
Claims 11-12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20130083615 (CHOI) in view of US 20200334119 A1 (LIM) and further in view of US 20080151647 (MILLER et al).
With respect to claim 11, CHOI teaches method for controlling a DRAM including a bitline sense amplifier shared by first bitlines of a first mat and second bitlines of a second mat adjacent to the first mat (dynamic random access memory device including first array of memory cells arranged at intersection by bitline and wordlines; second array of memory cells arranged in rows and columns and arranged at intersection of wordlines and bitlines; sense amplifiers disposed between the pairs of arrays, the sense amplifier being adjacent to a bitline concurrently connected) [Fig. 3A&3B; Par. 0053; Par. 0020] the method comprising: identifying memory usage and an application operation method of a server to which the DRAM belongs (method of operating the dynamic random access memory array comprising: pre-charging the plurality of bitlines to a reference voltage and connecting subset of the plurality of bitlines to respective sense amplifiers [Fig. 5; Par. 0066-0068; Par. 0055].
CHOI fails to specifically teach selecting one of a basic mode, a low-latency mode, or a low-power mode based on the memory usage and the application operating method; and controlling the first mat and the second mat according to the selected mode. However, LIM teaches memory devices arranged in groups and a system controller configured to control data input/output for each processing group, the system controller configured to include a power management device configured to configure (activate each group) at least one memory group of the plurality of memory devices based on predetermined power mode (based on an operating voltage characteristic) wherein the predetermined power modes include normal power mode, high speed with low latency mode in response to a request; and power saving mode being an inactive mode, [Abstract; Par. 0057-0061; Par. 0079-0080].
CHOI teaches (corresponding to the limitation the bitline sense amplifier connected to the first mat is shared only with the second mat) the sense amplifiers selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least complementary bitline of the second plurality of bitlines (the bitlines 112 coupled to two pairs of sense amplifiers 118 are interleaved, such that (as best seen in FIG. 5) bitlines 112A, 112C, 112E are coupled to one pair of sense amplifiers 118, and bitlines 112B, 112D, 112F are coupled to another pair of sense amplifiers 118) [Abstract; Fig. 5; Par. 0054; Par. 0020-0021].
Neither CHOI nor LIM specifically teaches the DRAM memory wherein the bitline sense amplifier connected to the first mat is shared only with the second mat. However, MILLER teaches a semiconductor memory device, such as a dynamic random access memory (DRAM) device, a sense amplifier provided where typically in DRAM, the sense amplifier is shared by first and second memory array segments to sense voltage on bitlines to either one memory array segment or the other memory array segment, but never sensing from both memory array segments at the same time [Par. 0002-0003; Par. 0020-0022]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing of the instant application to feature, within CHOI’s dynamic RAM, the application operating method, as taught by LIM, in order to provide the connection feature of the sense node pair of the sense amplifier to and disconnects the sense node pair from, the first memory array, as taught by MILLER [Par. 0003]. The result would provide specific memory device operation at regulated and defined voltage or speed that would improve information processing performance; as taught by LIM [Par. 0079-0080]. It would have further been obvious to feature, into the combination by CHOI and LIM, the bitline sense amplifier connected to the first mat is shared only with the second mat, taught by MILLER, in order to provide the connection feature of the sense node pair of the sense amplifier to and disconnects the sense node pair from, the first memory array, as taught by MILLER [Par. 0003].
With respect to claim 12, CHOI, LIM, and MILLER, combined teach the DRAM, wherein the bitline sense amplifier includes a first input terminal that is connected to one of the first bitlines and a second input terminal that is connected to one of the second bitlines corresponding to the first bitline connected to the first input terminal (each bitline selectively connects an active wordline at a memory cell is connected to a sense amplifier connected to a bit select line as input) [CHOI’s Fig. 5; Fig. 11; Par.0065].
With respect to claim 19, CHOI, LIM, and MILLER, combined teach the DRAM, wherein the second cell array stores opposite data or independent data of the first cell array (DRAM device having multiple arrays, each having DRAM cells arranged between wordlines and bitlines with sense amplifiers disposed between pairs of arrays and coupled to the bitlines via corresponding voltage input line) [CHOI’s Par. 0064-0065].
Allowable Subject Matter
Claims 4-9 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
S. M. Kim, B. Song and S. -O. Jung, "Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 6, pp. 2546-2554, June 2021.
H. Hidaka, Y. Matsuda and K. Fujishima, "A divided/shared bitline sensing scheme for 64 Mb DRAM core," Digest of Technical Papers., 1990 Symposium on VLSI Circuits, Honololu, HI, USA, 1990, pp. 15-16.
US 20180321865 A1 (WATKINS et a) operating mode being one of a plurality of operating modes of the application, wherein each operating mode of the plurality of operating modes corresponds to a different configuration of memory, the configurations of memory corresponding to different portions of memory that are active or inactive; and a memory control module configured to configure the memory based on the determined operating mode of the application.
US 20250124974 A1 (KWON et al) memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline.
US 20210335412 A1 (HE) teaching edge memory array mat with access lines that are split and a bank of sense amplifiers formed under the edge memory array may in a region that separates the access line segment halves, the sense amplifiers of the bank of sense amplifiers coupled to opposing ends of a first subset of the half access lines pairs; the edge memory array mat further including access line connectors configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached at (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
PIERRE MICHEL BATAILLE
Primary Examiner
Art Unit 2138
/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138