DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/312,608, filed on 05/05/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/25/2025, 12/01/2025 was filed and considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s submitted prior arts, Yamazaki et al., US 2018/0240421 A1, in view of Arasawa et al., US 2011/0299003 A1.
Regarding claim 1, Yamazaki et al. disclose a display device (figs 4, 5, 7, 10, 12) comprising:
. a substrate 14 (paper plan)
. a first pixel 11(i, j)
. a second pixel 11(i+1, j)
. a third pixel 11(i+2, j)
. a fourth pixel (i+3, j) , all are arranged in a first direction on the substrate (vertical direction)
. a first data signal line S1
. a second data signal line S3
. a third data signal line S2
. a fourth data signal line S4, wherein the first to fourth data signal lines extend in the first direction
. the first/third data signal lines including first/third upper conductive layers and first/third lower conductive layers ([0199]).
Yamazaki et al, however, neither disclose the first/third upper conductive layers connected to the first/third lower conductive layers via first/third contact holes, nor the first lower conductive layer intersects the third upper conductive layer in a plan view. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to employ a separated upper conductive layer and lower conductive layer and its connected via a contact hole, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179. In addition, Arasawa et al. do disclose a first data line 102B crosses a third data line 102A (fig. 3). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to employ the Yamazaki et al. first data signal line crossing third signal data line (so as first lower conductive layer crossing third upper conductive layer), as shown by Arasawa et al. to reduce deviation in the grayscale and/or signal delay in a display device ([0053]).
It is noted that the limitation of “the first to fourth pixels are simultaneously driven” recites a one-step of driven processing which does not further limit the structure of the device claims. Therefore, this limitation has not been given patentable weight.
Re claims 2-4, the modification to Yamazaki et al. would also result the first data signal line intersects the third data signal line in a plan view more than once, and the first pixel is located between the first intersecting area and the second intersecting area in the first direction, the first and second pixels are located between the first intersecting area and the second intersecting area in the first direction (fig. 3).
Re claims 5-6, wherein Yamazaki et al. also disclose a width of the first lower conductive layer is different (e.g., wider than) from a width of the third upper conductive layer (Yamazaki et al., fig. 21A, [0241]).
Re claims 7-10, Yamazaki et al. disclose the claimed invention as described above except for the second/fourth upper conductive layers connected to the second/fourth lower conductive layers via second/fourth contact holes, nor the second upper conductive layer intersects the second upper conductive layer in a plan view. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to employ a separated upper conductive layer and lower conductive layer and its connected via a contact hole, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. Nerwin v. Erlichman, 168 USPQ 177, 179. In addition, Arasawa et al. do disclose a first data line 102B crosses a third data line 102A (fig. 3). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to employ the Yamazaki et al. second data signal line crossing fourth signal data line (so as second upper conductive layer crossing fourth lower conductive layer), as shown by Arasawa et al. to reduce deviation in the grayscale and/or signal delay in a display device ([0053]).
Re claims 11-12, Yamazaki et al. also disclose a width of the lower conductive layer is different (e.g., wider than) from a width of the upper conductive layer, e.g., second upper conductive layer is different from a width of the fourth lower conductive layer (Yamazaki et al., fig. 21A, [0241]).
Re claims 13-16, Yamazaki also disclose the first pixel includes a first transistor connected to a first gate wiring and the first data signal line, the second pixel includes a second transistor connected to a second gate wiring and the second data signal line, the third pixel includes a third transistor connected to a third gate wiring and the third data signal line, the fourth pixel includes a fourth transistor connected to a fourth gate wiring and the fourth data signal line, and a scan signal is simultaneously sullied to the first to fourth gate wirings (Yamazaki et al., figs. 10-14).
Re claim 17, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel arranged in an order as listed, at least one pixel is located between the first pixel and the fourth pixel in the first direction, and the at least one pixel is different from the second pixel and the third pixel (Yamazaki et al., fig 10).
Re claim 18, wherein the first pixel is directly adjacent to the second pixel, the third pixel is directly adjacent to the fourth pixel, and pixels are located between the second pixel and the third pixel in the first direction (Yamazaki et al., fig 10).
Re claim 19, the modification to Yamazaki et al. disclose the claimed invention as described above of claims 1 and 7.
Re claim 20, wherein the first pixel includes a first transistor connected to the first data signal line, the second pixel includes a second transistor connected to the second data signal line, the third pixel includes a third transistor connected to the third data signal line, the fourth pixel includes a fourth transistor connected to the fourth data signal line (Yamazaki et al., fig 10).
It is also noted that the limitation of “the first to fourth transistors are simultaneously turned on” recites a one-step of driven processing which does not further limit the structure of the device claims. Therefore, this limitation has not been given patentable weight.
Conclusion
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/DUNG T NGUYEN/Primary Examiner, Art Unit 2871
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