DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 13 April 2026 and 23 April 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 8, 11-13, 15, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2022/0199170 A1 (Rayaprolu) in view of US Patent Application Publication No. US 2022/0398024 A1 (Ge) in further view of US 2013/0346805 A1 (Sprouse) in further view of US Patent Application Publication No. US 2023/0048514 A1 (Wu).
Regarding claim 1 and analogous claims 8 and 15:
Rayaprolu teaches, A system (100) comprising: an integrated circuit (IC) memory device comprising memory cells (memory device (140) (130) [Fig. 1] [0050-0053]); a volatile memory device (local memory (119) can include registers (volatile) and other memory for storing pointers, fetched data, etc. [0057]) and a processing device operatively coupled to the IC memory device and the volatile memory device (processor (117) [Fig. 1] [0056] [0062] configured to execute instructions stored in local memory (119) for performing the various disclosed functions), the processing device to perform operations comprising: detecting initiation of a power-down operation of the system (by disclosing detecting the host request to transition the system power state to the sleep state (1430), which may be a power-down request [0152] [0158]) and in response to detecting the initiation of the power-down operation and detecting that there are background operations to be performed (by teaching that the memory sub-system can request a deferral of the sleep state to perform calibration scan operations in a deferral time period prior to entering the sleep state, such as on the highest priority bins, such as the oldest or those with the highest error rate (1326) [0152] 0158] sending a signal to a host system coupled to the processing device, the signal to indicate to the host system to wait to complete the power-down operation until performing the background operations is complete (by teaching that during the deferral time period, the memory sub-system can perform the background calibration scan operations during the deferral period before the memory system is transitioned to the sleep state (power-down) (1326) [Fig. 13] [Fig. 14] [0043] [0152] [0158]).
Rayaprolu does not explicitly disclose, but Ge teaches a queue to store background refresh operations (by teaching that a controller (135) or a memory system controller (115) associated with the non-volatile memory (210) (corresponding to memory system (110)) may include a queue of pending maintenance operations, which may include refresh operations [0044] [0046]. The memory device (210) may be of a system (100) including a memory device (130) including a die (160) of blocks (170) and pages (175) of memory cells [0029-0034]. The controller (115) may include a local memory, which may include SRAM (volatile) memory that may be used by the memory controller [0027]) and in response to detecting the initiation of the power-down operation and detecting that one or more background refresh operations remain in the queue (by teaching that it is determined whether the quantity of pending maintenance operations exceeds a threshold, such as 0 (detecting that one or more refresh operations remain in the queue), in response to a request to transition to the lower-power sleep state (325), which may be a request to hibernate, which is a sleep mode [Fig. 3] [0010] [0066]. The controller (115) is coupled with the memory device (130) and includes the SRAM, which may be used for internal storage or calculations. The controller may also include a processor for performing the operations ascribed to the controller [0026-0027]. The memory controller receives the command for the non-volatile memory (310) to enter the low power state (320) [Fig. 3] [0065]. The controller may also determine a status, which may indicate a quantity of maintenance operations that are pending in the queue [0037] [0045-0054]) (detecting that one or more background refresh operations remain in the queue), and send that indication to a host, so that a host may determine a duration to delay sending a hibernate command so that the maintenance operations may be performed [0037] [0045-0054] [Fig. 2]); and sending a signal to a host system coupled to the processing device, the signal comprising a number of the refresh operations remaining in the queue to indicate to the host system to wait to complete the power-down operation until writing refresh data of the IC memory device is complete (by teaching that the non-volatile memory (310) (corresponding to memory system (110)), which may be the local or system controller for the memory, may send an indication of a duration (335) or a state of the maintenance operations (225) to a host system (205) (305) [Fig. 2] [Fig. 3] [0037] [0045-0047] [0067]. The indication of the duration is sent to the host system (305) so that the non-volatile memory (the local memory controller or system memory controller) may perform the maintenance operations, including refresh operations, within the duration indicated to the host system, such that they may be completed before transitioning to the low-power mode [Fig. 3] [0069-0071]. The memory system can indicate the duration to a host with a quantity of pending maintenance operations, and the host may determine a duration based on the quantity of pending maintenance operations (which may be pending in a queue) [0045-0049]. The determined duration may be used to delay the entry into a hibernation mode so that the maintenance operations may be completed before transitioning the memory device to the next power state [0045-0054] [Fig. 2] [Fig. 3]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified detecting the command to transition to the power-down sleep state and asking the host to defer the sleep state as taught by Rayaprolu to include determining whether any background refresh operations are pending in a queue and sending the host a number of the operations pending in the queue, so that the host may determine an appropriate amount to delay the transition to the next power state, and then performing the background refresh operations within the requested wait time before the system transitions to the next power state as taught by Ge.
One of ordinary skill in the art would have been motivated to make this modification because allowing for maintenance operations to be completed before entering a lower power mode according to a determined duration may delay the latency with which maintenance operations are performed and may improve performance without degrading performance of host commands or increasing power consumption as it allows more commands to be performed before entering the next power state as taught by Ge in [0016] [0039].
Rayaprolu in view of Ge does not explicitly disclose, but Sprouse teaches, a volatile memory comprising a queue to store indicators for one or more blocks of the memory cells qualified for refresh based on one or more sampling background scans of a plurality of blocks of memory cells of the IC memory device, such that detecting remaining refresh operations (as taught by Ge) and a number of refresh operations (as taught by Ge) would include detecting one or more indicators remain in the queue corresponding to the one or more blocks of the memory cells, and a number of one or more indicators remaining in the queue, and waiting for refresh operations to complete would include waiting for writing refresh data from the one or more blocks, to one or more erased blocks of the IC memory device (by teaching that when the errors in a scanned wordline are above a threshold (808 -> Yes), the blocks are placed in a refresh queue (810) [Fig. 8], such that the refresh operations for the block can be performed as a background process at a later time [0004]. The refresh queue may be stored in the controller RAM [0050]. The background refresh process includes copying data from the blocks to new (erased) blocks [0004] [0030] [0042] [0050] [Fig. 13]. The background process should be performed at a later time when it will not interfere with the device’s ability to respond to host commands [0042] [Fig. 8]) such that the queue becoming empty would involve the queue being empty of the one or more indicators and completing all commands would mean that the queue is empty (by teaching that when the errors in a scanned wordline are above a threshold (808 -> Yes), the blocks (identifiers) are placed in a refresh queue (810) [Fig. 8], such that the refresh operations for the block can be performed as a background process at a later time [0004]. The refresh queue may be stored in the controller RAM [0050]. The background refresh process includes copying data from the blocks to new (erased) blocks [0004] [0030] [0042] [0050] [Fig. 13]. The background process should be performed at a later time when it will not interfere with the device’s ability to respond to host commands [0042] [Fig. 8]. It is understood that the queue would be empty if there are no blocks stored in it according to the example queue seen in [Fig .12] with block identifiers stored within it [0050], and that the queue would be empty when all the queued operations have been completed).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pending background operations queue including refresh operations as taught by Rayaprolu in view of Ge to include blocks targeted for refresh that have a threshold bit error level and stored in a refresh queue, such as in a controller RAM (volatile SRAM as taught by Ge) such that the blocks can have a refresh operation performed on them at a later time (such as after a request to power-down but before powering-down as taught by Rayaprolu in view of Ge) including copying valid data to a new erased block so that the background refresh operations don’t interfere with the device’s ability to respond to commands from the host as taught by Sprouse.
One of ordinary skill in the art would have been motivated to make this modification because placing blocks in the refresh queue based on a determined number of errors to refresh at a later time avoids reducing performance and life of the memory by refreshing a block too frequently, and allows the blocks to be refreshed at a later time when it does not interfere with the device’s ability to respond to host commands as taught by Sprouse in [0042-0043].
Rayaprolu in view of Sprouse does not explicitly disclose, but Wu teaches, wherein the operations further comprise: monitoring the pending maintenance commands to determine when the pending maintenance commands are complete (i.e., monitoring the queue to detect when the queue becomes empty of the one or more indicators as taught in combination with Sprouse) and in response to detecting that the media management operations are complete (i.e., and in response to detecting that the queue is empty as taught in combination with Sprouse), informing the host system to complete the power-down operation (by disclosing that a memory sub-system may receive indication of a shutdown operation (470). In response, the memory system may enter a pre-shutdown mode (472) and initiate media management operations for the memory system while in the pre-shutdown mode (474). When the media management operations are complete (i.e., such as when the queue of refresh operations taught by Sprouse is empty), the memory sub-system may send a completion response to the host and the host may then shutdown the memory sub-system. The media management operation may be a refresh operation [Fig. 4] [0013] [0034] [0036] [0047] [0051-0053] [0056]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the shutdown of the memory sub-system as taught by Rayaprolu in view of Ge in further view of Sprouse to include waiting for the memory sub-system to indicate to the host that pending operations (such as those stored in the refresh queue as taught by Sprouse) are complete as taught by Wu.
One of ordinary skill in the art would have been motivated to make this modification because the completion message back to the host allows the system as a whole to finalize the shutdown process, and may improve the memory sub-system performance and reliability without interrupting important functionality by the memory sub-system when it is in a normal operation (i.e., not shutting down) as taught by Wu in [0013].
Regarding claim 4 and analogous claims 11 and 17:
The system of claim 1 is made obvious by Rayaprolu in view of Ge in further view of Sprouse in further view of Wu (Rayaprolu-Ge-Sprouse-Wu).
Rayaprolu in view of Ge do not explicitly disclose, but Sprouse teaches, wherein the operations further comprise: performing one or more sampling background scans of the one or more blocks to determine a representative error rate of each respective block of the memory cells; and determining, based on the representative error rate for each respective block, that the one or more blocks qualify for refresh (by teaching that wordlines in a block may be scanned with a read scrub scan (sampling background scan) [0040]. The read scrub scans may be performed for each block or wordline according to a determined frequency [0044-0045]. When the errors in a scanned wordline are above a threshold (808 -> Yes), the blocks are placed in a refresh queue (810) [Fig. 8], such that the refresh operations for the block can be performed as a background process at a later time [0004]. The refresh queue may be stored in the controller RAM [0050]. The background refresh process includes copying data from the blocks to new (erased) blocks [0004] [0030] [0042] [0050] [Fig. 13]. The background process should be performed at a later time when it will not interfere with the device’s ability to respond to host commands [0042] [Fig. 8]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pending background operations queue including refresh operations as taught by Rayaprolu in view of Ge to include blocks targeted for refresh that have a threshold bit error level, as determined by a periodic read scrub scan, and stored in a refresh queue, such as in a controller RAM (volatile SRAM as taught by Ge) such that the blocks can have a refresh operation performed on them at a later time (such as after a request to power-down but before powering-down as taught by Rayaprolu in view of Ge) including copying valid data to a new erased block so that the background refresh operations don’t interfere with the device’s ability to respond to commands from the host as taught by Sprouse.
One of ordinary skill in the art would have been motivated to make this modification because placing blocks in the refresh queue based on a determined number of errors to refresh at a later time avoids reducing performance and life of the memory by refreshing a block too frequently, and allows the blocks to be refreshed at a later time when it does not interfere with the device’s ability to respond to host commands as taught by Sprouse in [0042-0043].
Regarding claim 5 and analogous claims 12 and 18:
The system of claim 1 is made obvious by Rayaprolu-Ge-Sprouse-Wu.
Rayaprolu does not explicitly disclose, but Ge teaches, wherein the operations further comprise determining, based on a number and data type of the one or more blocks, an amount of time to perform the pending commands, and wherein the signal includes the amount of time to empty the queue so that the host system can wait to complete the power-down operation for the amount of time to perform the pending commands (by teaching that the memory system controller may estimate a duration for performing the one or more pending maintenance operations on the non-volatile memory (310), based on an indication of the maintenance operations to be performed, and an urgency of the pending operations (data type of one of the blocks) [0067]. The estimated duration may then be transmitted to the host in order to delay entering the low-power mode [0067] [0071]).
Ge does not explicitly disclose, but Sprouse teaches that the pending refresh operations are stored in a queue, such that determining an amount of time to perform them as taught by Ge would include determining an amount of time to empty the queue (by teaching that wordlines in a block may be scanned with a read scrub scan (sampling background scan) [0040]. The read scrub scans may be performed for each block or wordline according to a determined frequency [0044-0045]. When the errors in a scanned wordline are above a threshold (808 -> Yes), the blocks are placed in a refresh queue (810) [Fig. 8], such that the refresh operations for the block can be performed as a background process at a later time [0004]. The refresh queue may be stored in the controller RAM [0050]. The background refresh process includes copying data from the blocks to new (erased) blocks [0004] [0030] [0042] [0050] [Fig. 13]. The background process should be performed at a later time when it will not interfere with the device’s ability to respond to host commands [0042] [Fig. 8]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the pending background operations queue including refresh operations as taught by Rayaprolu in view of Ge to include blocks targeted for refresh that have a threshold bit error level, as determined by a periodic read scrub scan, and stored in a refresh queue, such as in a controller RAM (volatile SRAM as taught by Ge) such that the blocks can have a refresh operation performed on them at a later time (such as after a request to power-down but before powering-down as taught by Rayaprolu in view of Ge) including copying valid data to a new erased block so that the background refresh operations don’t interfere with the device’s ability to respond to commands from the host as taught by Sprouse.
One of ordinary skill in the art would have been motivated to make this modification because placing blocks in the refresh queue based on a determined number of errors to refresh at a later time avoids reducing performance and life of the memory by refreshing a block too frequently, and allows the blocks to be refreshed at a later time when it does not interfere with the device’s ability to respond to host commands as taught by Sprouse in [0042-0043].
Regarding claim 6 and analogous claims 13 and 19:
The system of claim 5 is made obvious by Rayaprolu-Ge-Sprouse-Wu.
Rayaprolu does not explicitly disclose, but Ge teaches, wherein the signal further includes a flag that specifies an urgency level associated with the refresh so that the host system can decide whether to wait or proceed with the power-down operation (by teaching that the memory system controller may indicate an urgency to the host with a level indicating a level of dirtiness of the non-volatile memory. Based on the level sent to the host, the host may determine the amount of time to delay the transition to the sleep mode (whether to wait or proceed with the power-down operation) [0046-0049]. The non-volatile memory may also communicate the urgency or level of dirtiness, which corresponds with the number of pending commands that are queued and yet to be performed [0046-0047]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified asking the host to defer the sleep state as taught by Rayaprolu to include sending the host an urgency level, such that the host can determine an amount of time to delay the memory system based on the sent urgency level as taught by Ge.
One of ordinary skill in the art would have been motivated to make this modification because allowing for maintenance operations to be completed before entering a lower power mode may delay the latency with which maintenance operations are performed and may improve performance without degrading performance of host commands or increasing power consumption as taught by Ge in [0016].
Claims 2-3, 9-10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Rayaprolu-Ge-Sprouse-Wu in further view of US Patent Application Publication No. US 2024/0070017 A1 (Wang) in further view of US Patent Application Publication No. US 2021/0342074 A1 (Reina).
Regarding claim 2 and analogous claims 9 and 16:
The system of claim 1 is made obvious by Rayaprolu-Ge-Sprouse.
Rayaprolu does not explicitly disclose, but Wang teaches, wherein the operations further comprise: performing one or more sampling background scans of the one or more blocks; and determining that the one or more blocks have a retention time based on at least one attribute of self-monitoring analysis and reporting technology (S.M.A.R.T.) data obtained from the one or more sampling background scans (by teaching that based on periodic scans, the raw bit error rate (RBER) of blocks may be measured and then used to estimate a retention time remaining before the RBER reaches a threshold level. The retention time may be saved as part of a SMART log. The user may then be warned of the estimated data retention time in a notification service [0068-0075] [Fig. 6]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system as taught by Rayaprolu-Ge-Sprouse to include performing periodic scans to determine RBER and retention time of a block as taught by Wang.
One of ordinary skill in the art would have been motivated to make this modification because estimating the retention time from RBER and notifying the customer of the estimated data retention time can ensure that customers are informed of critical times as taught by Wang in [0026].
Wang does not explicitly disclose, but Reina teaches, that it can be determined whether blocks qualify for refresh based on a retention time (i.e., at least one attribute of self-monitoring analysis and reporting technology (S.M.A.R.T.) data as taught by Wang) (by teaching that a block of memory may be automatically refreshed according to a retention time limit of a memory [0041] [0061]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the use of the retention time stored in the SMART log as taught by Wang to be used to trigger an automatic refresh as taught by Reina (such as by placing the block in the refresh queue as taught by Sprouse).
One of ordinary skill in the art would have been motivated to make this modification because it would allow the system to evaluate when a region of the non-volatile memory has to be refreshed to avoid corruption or loss of data as taught by Reina in [0005].
Regarding claim 3 and analogous claim 10:
The system of claim 2 is made obvious by Rayaprolu-Ge-Sprouse-Wu in further view of Wang in further view of Reina.
Rayaprolu-Ge-Sprouse-Wu in further view of Wang in further view of Reina further make obvious, wherein the at least one attribute comprises one or more of total bytes written (TBW), temperature change over time, or a data state metric (through the analysis performed for claim 2 because the “retention time” taught and used by Wang in view of Reina is a data state metric).
Response to Arguments/Amendments
In response to Applicant’s arguments, the 35 USC §112(a) rejection has been withdrawn.
In response to Applicant’s arguments, the 35 USC §103 rejection has been updated to include a rejection of the amended subject matter with Wu. Although this subject matter was present in now cancelled claims 7, 14 and 20 and previously rejected with a combination of references including Wu, Applicant provides no argument against the rejection with the combination of references including Wu. Therefore, the Examiner has updated the rejection to include the combination of references including Wu. As Applicant’s arguments are not directed to any particular deficiency of Wu in combination with the other references (Rayaprolu, Ge, and Sprouse), Applicant’s arguments are not persuasive.
Applicant also argues that “Sprouse teaches that the later time for refreshing blocks in the queue may be based on the initiation of a housekeeping operation such as garbage collection or other background operations that do not interfere with the device’s ability to respond to host commands. (Id.) This is unrelated to power-down operations and does not suggest the claimed coordination between the memory sub-system and the host during power-down.” However, the Examiner did not rely upon Sprouse to teach the coordination between the memory sub-system and the host during power-down. Instead, the Examiner relied upon Rayaprolu and Ge to teach the coordination between the memory system and the host during power-down, and relied upon Sprouse to provide the structure of the queue that stores indicators of refresh operations that may be performed at a later time (such as at power-down as taught by Rayaprolu in view of Ge) and therefore Applicant’s arguments against the references individually are not persuasive.
Applicant argues that Rayaprolu, Ge, and Sprouse fail to teach in response to detecting the initiation of the power-down operation and detecting that one or more indicators remain in the queue corresponding to the one or more blocks of the memory system, sending a signal to a host system…” However, the Examiner respectfully disagrees, as the references teach the combination as seen in the corresponding rejection section above. Applicant provides no specific deficiency in any of the references such that the combination would not render the limitation obvious as laid out in the rejection above, and accordingly, Applicant’s mere assertion is not persuasive.
Applicant argues that Rayaprolu, Ge, and Sprouse fail to teach the monitoring of the queue to detect when it is empty and informing the host to complete the power-down operation when the queue is determined to be empty. However, the Examiner finds that these limitations are obvious in view of the combination of Rayaprolu, Ge, and Sprouse in further view of Wu. Applicant makes no arguments regarding this combination, and accordingly, Applicant arguments against a subset of references that are not used alone to render obvious the claimed limitations (but instead further rely upon Wu) are not persuasive.
As Applicants arguments were not persuasive, the claims are not indicated as allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent No. US 11,017,823 B1 (Kamepalli) – teaches to delay a power down operation based on an amount of data in volatile memory [Fig. 2].
US Patent Application Publication No. US 2023/0401005 A1 (Muthiah) – teaches to estimate a completion time of a plurality of queued operations including background operations [Figs. 7-8] [0059-0061]. It also teaches to issue commands from a queue until it is empty and then to issue commands from a lower priority queue [0061].
US Patent Application Publication No. US 2025/0272146 A1 (Segev) – teaches to empty a queue in response to a shutdown notification from a host by sending error notifications to the host that the commands did not complete so that the storage device may shutdown more quickly [Fig. 8] [0054-0059].
US Patent Application Publication No. US 2017/0068480 A1 (Huang) – teaches the storage device checking whether the command queues are empty before going to sleep and then saves the commands to non-volatile memory when they are not empty so that when the storage device is woken again, the host then commands the storage device to complete the pending commands that were saved to non-volatile memory. When the storage device command queues are empty, it will go to sleep [Fig. 4] [0032].
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/CURTIS JAMES KORTMAN/Primary Examiner, Art Unit 2139
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