DETAILED ACTION
This office action is in response to a Request for Continued Examination (RCE) filed 5/28/2026 for application 18/935,952 filed 11/4/2024 that claims priority to provisional application 63/691,225 filed 9/5/2024.
Claims 1, 11 and 17 have been amended. Claim 8 has been cancelled. No claims are new. Thus claims 1-7, and 9-21 have been examined.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6, 9-13, 16-17, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Hily (Hily et al., US 2023/0176749) and further in view of Mutlu (A publication titled “18-447 Computer Architecture Lecture 21: Main Memory” by Prof Onur Mutlu, Carnegie Mellon University, Spring 015, 3/23/2015) and Johnson (Johnson US 2003/0110205 A1).
Regarding claim 1 system comprising: (Hily Fig. 2 and [0031] discloses Computer System 100.) a memory controller; (Hily Fig. 2 and [0027] and [0031] that discloses memory control circuits MMC) 118 where each MMC is an example of a memory controller control sending data to a memory channel (channel 0 and/or 1) that are attached to memory chips 110,) and a memory circuit coupled to the memory controller, (Hily Fig. 2 and [0031] that discloses DRAM chips 110 that are coupled to memory control circuits MMC 118)
wherein the memory controller is configured to determine whether to mirror data on a command-by-command basis, (Hily Abstract, Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is within a listed address range it will mirror the data to memory associated with separate channels, otherwise it will write the data a single time to a single channel. Thus the system determines whether to mirror data on a write command-by-command basis.)
wherein, in determining whether to mirror data, the memory controller is configured to: receive a first write command and a second write command; (Hily Fig. 3 and [0031]-[0036] that disclose there may be a plurality of commands and the commands may be write commands.)
decode a first address associated with the first write command, and decode a second address associated with the second write command; (Hily Fig. 3 and [0031]-[0036] most notably steps 304 and 308 that discloses there may be a first and second write command and for each inbound write request received the system reads the address associated with the request and where each address is read/decoded to determine how the data to write is to be processed. )
and wherein the memory controller is further configured to: in response to a determination of the first code having a first value, write data associated with the first write command to the first rank and the second rank; and (Hily Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is within a listed address range it will mirror the data to memory chips associated with a first and channels (i.e. separate channels).)
in response to a determination of the second code having a second value, write the data associated with the second write command to a single one of first and second ranks. (Hily Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is not within a listed address range it will write the data a single time to a single channel.)
However, Hily does not explicitly teach wherein the memory circuit comprises a dual-rank memory having a first rank and a second rank separately addressable from one another
wherein a subset of bits of the first address comprises a first code, and wherein other bits of the first address indicate a location within the memory circuit in which data associated with the first write command is to be stored;
wherein a subset of bits of the second address comprises a second code, and wherein other bits of the second address indicate a location within the memory circuit in which data associated with the second write command is to be stored;
determination of the first code having a first value, … a determination of the second code having a second value,
… write data .. to the first rank and the second rank… write the data.. to a single one of a first and second ranks…
Mutlu, of a similar field of endeavor, further teaches wherein the memory circuit comprises a dual-rank memory having a first rank and a second rank separately addressable from one another; … write data .. to the first rank and the second rank… write the data.. to a single one of a first and second ranks… (Mutlu page 78 discloses that DRAM memory, such as the DRAM of Hily, is organized by Channels that are made up of separate and distinct DIMMs that are in turn made up of separate and distinct ranks. See the diagram from page 78 of Mutlu included below for convenience:
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Examiner notes the target of any write is the cells targeted by the write command. When one issues a write to a channel, it identifies the appropriate DIMM, Rank, Chip, Bank, Row/Column array, and cells for the write and write to the appropriate DIMM, Rank, Chip, Bank, Row/Column array, and cells. Each channel has its own separate and distinct DIMMs, its own separate and distinct ranks, etc.. Thus Hily that teaches mirrored data is directed to different channels according to the memory address of the write request will write to different (i.e. separate and distinct) ranks within the separate channels.
Mutlu pages 78 and 74 that a single memory channel may be compose of a single DIMM, that contains a first rank on the front of the DIMM and a second rank on the back of a DIMM. Examiner notes that a dual-rank memory is a memory containing a first rank and separate rank. Thus the memory of Hily that contains memory associated with a first channel and a second channel is memory associated with two separate ranks and is multi-rank memory. See also Mutlu page 87 lines 1-7 that discloses that the bits in the address discloses which bank an target address is located in. Thus given the bank is within a rank that is within a separate channel, they are directed to separate first and second ranks separately addressable.)
Hily and Mutlu are in a similar field of endeavor as both relate to processing memory requests at a RAM memory, including DRAM memory (a form of RAM memory), including DDR4 memory (a form of DRAM). Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to recognize that directing write requests to separate channels of Hily is in fact directing the write requests to separate ranks based on the teachings of Mutlu. Thus combining prior art elements according to known methods (recognizing that channels are made up of ranks as taught by Mutlu to the teachings of Hily that directs mirrored data to separate channels) to yield predictable results (implementing DIMM memory according to well-known methods as taught by educational facilities in their computer architecture lectures directed to main memory in schools such as the Carnegie Mellon University.)
The motivation to combine Mutlu into Hily for claims 2-10 are the same as those set forth in claim 1 above.
However, the combination of Hily and Mutu does not explicitly teach wherein a subset of bits of the first address comprises a first code, and wherein other bits of the first address indicate a location within the memory circuit in which data associated with the first write command is to be stored;
wherein a subset of bits of the second address comprises a second code, and wherein other bits of the second address indicate a location within the memory circuit in which data associated with the second write command is to be stored;
determination of the first code having a first value, … a determination of the second code having a second value,
Johnson, of a similar field of endeavor, further teaches wherein a subset of bits of the first address comprises a first code, and wherein other bits of the first address indicate a location within the memory circuit in which data associated with the first write command is to be stored; (Hily Abstract, Fig. 3 and [0032]-[0036] discloses write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. Johnson Fig. 1 and [0010]-[0013] teaches that a range of addresses such as address range 112 may be referenced by the physical memory block and the page. Johnson [0079]-[0080] discloses each memory control hardware may manage a range of blocks, and to address a specific address the address includes a module number 806a, block number 806b, and offset 806c, where address ranges are specified by the module number and block number. Thus the address of the first write of Hily that specifies the write address will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored, and a third field (a second code) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the first write command).)
wherein a subset of bits of the second address comprises a second code, and wherein other bits of the second address indicate a location within the memory circuit in which data associated with the second write command is to be stored; (See Hily Fig. 3 and [0031]-[0036] and Johnson Fig. 1 and [0010]-[0013] and [0079]-[0080] that discloses the second address for the second write command will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored, and a third field (a second code) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the second write command).)
determination of the first code having a first value, … a determination of the second code having a second value, (See Hily Fig. 3 and [0031]-[0036] and Johnson Fig. 1 and [0010]-[0013] and [0079]-[0080] as detailed immediately above that discloses each write request contains an address containing first and middle field that are decoded from the first and second write requests to produce a first code and second code respectively.
Hily, Mutlu, and Johnson are all in a similar field of endeavor as both relate to processing memory requests at a RAM memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate module, block and page addressing for memory controller ranges as taught by Johnson into the solution of Hily and Mutlu that accesses memory via memory controllers for specific ranges. Thus combining prior art elements according to known methods to achieve predictable results (To provide a means of memory mapping that enable a system to remap a range of physical memory addresses from one machine (hardware) memory resource to another without requiring the server to be rebooted. Thus providing hardware recovery without the delay expense associated with rebooting a server.).
The motivation to combine Johnson into the combination of Hily and Mutlu for claims 2-10 are the same as those set forth in claim 1 above.
Regarding claim 4, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 1 above. Hily further teaches wherein the memory controller is further configured to, in response to receiving a read command to read the data associated with the first write command, and based on the first value: read the data associated with the first write command from the first rank; (Hily [0040] discloses that when a read request arrives the system examines the memory read address and directs the read request to the primary read data in the primary memory channel. Thus Hily reads data associated with the first write command that was previously written, based on the address of the read command and the address of the previously write address, and reads the data from the primary channel containing a primary (i.e. first) rank in the solution of Hily in view of Mutlu.)
determine a presence of an error in the data associated with the first write command; and in response to determining the presence of the error, read the data associated with the first write command from the second rank. (Hily [0040] discloses that when a read request arrives the system examines the memory read address and directs the read request to the primary read data in the primary memory channel, and directs the data to the secondary memory channel if an error occurs on the primary channel. Thus Hily in view of Mutlu reads data associated with the first write command that was previously written, based on the address of the read command and the address of the previously write address, and reads the data from the second rank in the second channel in response to the presence of an error on the first rank/channel.)
Regarding claim 6, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 1 above. Hily further teaches wherein the memory controller is further configured to forego providing error protection to the data associated with the second write command in response to the second code having the second value. (Hily Abstract, Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is not within a listed address range establish by the first and middle segments (the second code for the second write) it will write the data a single time to a single channel and error protection through mirroring is not performed (to forego).)
Regarding claim 9, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 1 above.
Hily in view of Mutlu and Johnson further teaches wherein the memory controller is configured to, for a given write command, decode an address comprising a first plurality of bits and a second plurality of bits, wherein the first plurality of bits of the address indicates a location within the memory circuit in which data associated with the given write command is to be stored, the second plurality bits associated with the given write command indicate whether the data associated with the given write command is to be stored in both the first and second ranks. (Hily [0003] discloses the system used the address of the data in the system memory, thus uses the physical address of the write. Johnson Fig. 1 and [0010]-[0013] teaches that a range of addresses such as address range 112 may be referenced by the physical memory block and the page. Johnson [0079]-[0080] discloses each memory control hardware may manage a range of blocks, and to address a specific address the address includes a module number 806a, block number 806b, and offset 806c, where address ranges are specified by the module number and block number. Thus the address of Hily that specifies the write address will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored to a first and second channel (thus to a first and second rank) and are an example of a second plurality of bits, and a third field (a second code) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the first write command) and are an example of a fist plurality of bits.)
The motivation to combine Johnson into the existing combination is the same as set forth in claim 1 above.
Regarding claim 10, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 9 above.
Hily in view of Mutlu and Johnson further teaches in response to receiving a given read command corresponding to the given write command, the memory controller is configured to determine, based on the second plurality of bits, one or more parameters for reading the data associated with the given write command from the memory circuit. (Hily discloses that the solution of Hily uses the address of a read command to previously written data such as the given write command, to determine where the data is to be read. Johnson Fig. 1 and [0010]-0013] and [0079]-[0080[ further teaches the address includes both a first and middle field (a first code that is a second plurality of bits) used to determine if the data is written to a primary and backup channel. Thus Hily in view of Johnson will determine if the data is to be read from mirrored data based on the second plurality of bits that indicate if the data was mirrored.)
The motivation to combine Johnson into the existing combination is the same as set forth in claim 1 above.
Regarding claim 11, Hily teaches A method comprising: (Hily [0005] discloses that the inventive concepts may be directed to methods in a mirroring computer system.)
receiving, at a memory controller, (Hily Fig. 2 and [0026]-[0027] and [0031] that discloses memory control circuits MMC) 118 where each MMC is an example of a memory controller control sending data to a memory channel (channel 0 and/or 1) that are attached to memory chips 110,) first and second write commands to write respective data to a memory circuit coupled to the memory controller, (Hily Fig. 3 and [0031]-[0036] most notably steps 304 and 308 that discloses there may be a first and second write command and for each inbound write request received the system reads the address associated with the requests to DRAM Chip 110. )
determining, for the first write command and the second write command, whether to mirror data on a command-by-command basis, (Hily Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the incoming write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is within a listed address range it will mirror the data to memory associated with separate channels, otherwise it will write the data a single time to a single channel. )
decoding, using the memory controller, a first address associated with the first write command, (Hily Abstract, Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored, wherein the address of the write request is a first address).
decoding, using the memory controller, a second address associated with the second write command, (Hily Fig. 3 and [0031]-[0036] most notably steps 304 and 308 that discloses there may be a first and second write command and for each inbound write request received the system reads the address associated with the request and where each address is an example of a code that determines how the data to write is to be processed. )
writing, using the memory controller and in response to determining the first code has a first value data associated with the first write command into the first rank and the second rank, and (Hily Abstract, Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is within a listed address range it will mirror the data to memory chips associated with two separate channels.)
writing, using the memory controller and in response determining that the second code having a second value, data associated with the second write command to a single one of the first and second ranks. (Hily Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is not within a listed address range it will write the data a single time to a single channel/rank of a plurality of channels/ranks.)
However, Hily does not explicitly teach wherein the memory circuit comprises a dual-rank memory having a first rank and a second ranks separately addressable from one another;
wherein a subset of bits of the first address comprises a first code, and wherein other bits of the first address indicate a location within the memory circuit in which data associated with the first write command is to be stored;
wherein a subset of bits of the second address comprises a second code, and wherein other bits of the second address indicate a location within the memory circuit in which data associated with the second write command is to be stored;
… determining the first code has a first value … determining the second code has a second value
… the first write command into the first rank and the second rank, and writing … to a single one of the first and second ranks.
Mutlu, of a similar field of endeavor, further teaches wherein the memory circuit comprises a dual-rank memory having a first rank and a second ranks separately addressable from one another; … the first write command into the first rank and the second rank, and writing … to a single one of the first and second ranks. (Mutlu page 78 discloses that DRAM memory, such as the DRAM of Hily, is organized by Channels that are made up of DIMMs that are in turn made up of ranks See also Mutlu pages 78 and 74 that a single memory channel may be compose of a single dim, that contains a first rank on the front of the DIMM and a second rank on the back of a DIMM. Thus Hily that teaches mirrored data is directed to different channels according to the memory address of the write request will write to different separate ranks within the separate channels. Examiner notes that a dual-rank memory is a memory containing a first rank and separate rank. Thus the memory of Hail that contains memory associated with a first channel and a second channel is memory associated with two separate ranks and is multi-rank memory. See also Mutlu page 87 lines 1-7 that discloses that the bits in the address discloses which bank an target address is in. Thus given the bank is within a rank that is within a channel based on separate addresses in separate channels, the first and second rank are separately addressable from one another and when the system writes to separate first and second channels it is writing to separate first and second ranks.
Hily and Mutlu are in a similar field of endeavor as both relate to processing memory requests at a DRAM memory, including DDR memory such as DDR4. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to recognize that direction write requests to separate channels of Hily is directing the write requests to separate ranks as taught by Mutlu. Thus combining prior art elements according to known methods (recognizing that channels are made up of ranks as taught by Mutlu to the teachings of Hily that directs mirrored data to separate channels) to yield predictable results (implementing DIMM memory according to well-known methods as taught by educational facilities in their computer architecture lectures directed to main memory in schools such as the Carnegie Mellon University.)
The motivation to combine Mutlu into Hily for claims 2-10 are the same as those set forth in claim 1 above.
However, Hily and Mutlu does not explicitly teach teaches wherein a subset of bits of the first address comprises a first code, and wherein other bits of the first address indicate a location within the memory circuit in which data associated with the first write command is to be stored; wherein a subset of bits of the second address comprises a second code, and wherein other bits of the second address indicate a location within the memory circuit in which data associated with the second write command is to be stored; … determining the first code has a first value … determining the second code has a second value
Johnson, of a similar field of endeavor, further teaches wherein a subset of bits of the first address comprises a first code, and wherein other bits of the first address indicate a location within the memory circuit in which data associated with the first write command is to be stored; (Hily Abstract, Fig. 3 and [0032]-[0036] discloses write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. Johnson Fig. 1 and [0010]-[0013] teaches that a range of addresses such as address range 112 may be referenced by the physical memory block and the page. Johnson [0079]-[0080] discloses each memory control hardware may manage a range of blocks, and to address a specific address the address includes a module number 806a, block number 806b, and offset 806c, where address ranges are specified by the module number and block number. Thus the address of Hily that specifies the write address will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored, and a third field (a second code) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the first write command).)
wherein a subset of bits of the second address comprises a second code, and wherein other bits of the second address indicate a location within the memory circuit in which data associated with the second write command is to be stored; (Hily Fig. 3 and [0031]-[0036] that disclose there may be a plurality of commands and the commands may be write commands. Thus there may be a second write command with a second address. Thus as detailed immediately above, there may be a second write command to determine if the second write should be mirrored or not based on an address range. Johnson Fig. 1 and j[0010]-[0013] and [0079]-[0080] discloses the second address for the second write command will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored, and a third field (a second code) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the second write command).)
… determining the first code has a first value … determining the second code has a second value(See Hily Fig. 3 and [0031]-[0036] and Johnson Fig. 1 and [0010]-[0013] and [0079]-[0080] as detailed immediately above that discloses each write request contains an address containing first and middle field that are decoded from the first and second write requests to produce a first code and second code respectively.
Hily, Mutlu, and Johnson are all in a similar field of endeavor as both relate to processing memory requests at a RAM memory. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate module, block and page addressing for memory controller ranges as taught by Johnson into the solution of Hily and Mutlu that accesses memory via memory controllers for specific ranges. Thus combining prior art elements according to known methods to achieve predictable results (To provide a means of memory mapping that enable a system to remap a range of physical memory addresses from one machine (hardware) memory resource to another without requiring the server to be rebooted. Thus providing hardware recovery without the delay expenses associated with rebooting a server.).
The motivation to combine Johnson into the combination of Hily and Mutlu for claims 12-16 are the same as those set forth in claim 11 above.
Regarding claim 12, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 11 above. Hily further teaches further comprising: decoding a first address associated with the first write command, (Hily Fig. 3 and [0031]-[0036] most notably steps 304 and 308 that discloses there may be a first and second write command and for each inbound write request received the system reads the address associated with the request and where each address is an example of a code that determines how the data to write is to be processed.)
and decoding a second address associated with the second write command, (Hily Fig. 3 and [0031]-[0036] most notably steps 304 and 308 that discloses there may be a first and second write command and for each inbound write request received the system reads the address associated with the request and where each address is an example of a code that determines how the data to write is to be processed.)
Johnson further teaches wherein a subset of bits of the first address comprises the first code; wherein a subset of bits of the second address comprises the second code. (Johnson Fig. 1 and j[0010]-[0013] and [0079]-[0080] discloses the first address for the first write and the second address for the second write command will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored. Thus the subset of bits of the first address of the first write comprise the first code and the subset of bits of the second address of the second write comprise the second code in the solution of Hily in view of Mutlu and Johnson.
The motivation to combine Johnson into the existing combination is the same as set forth in claim 11 above.
Regarding claim 13, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 11 above. Hily further teaches further comprising: determining, by the memory controller, one or more read parameters for data associated with the first write command based on the first value, (Hily [0040] discloses read requests contain an address associated with the data to be read, which may be the same address of a previous write where an address within a read command is a read parameter for data associated with the first write command which may be to same address.)
wherein the one or more read parameters include determining from which of the first and second ranks the data associated with the first write command is to be read. (Hily [0040] discloses that the address (i.e. the read parameters) determines that the system should read the data from the primary read address and then goes to the read address associated with the secondary copy at a secondary address which would have been written to the second rank in the solution of Hily in view of Mutlu and Johnson.)
Regarding claim 16, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 11 above. Hily further teaches further comprising forgoing error protection for data associated with the second write command. (Hily Fig. 3 and [0032]-[0036] most notably steps 304 and 308 that for each inbound write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. If the address of the write request is not within a listed address range it will write the data a single time to a single channel. When data is written based on the address in the second write request to only one of the columns/ranks error protection through mirror is skipped/forgone.)
Regarding claim 17, Hily teaches A system comprising: (Hily [0005] discloses the inventive concepts are directed to a memory mirroring computer system.)
a memory controller; and (Hily Fig. 2 and [0027] and [0031] that discloses memory control circuits MMC) 118 where each MMC is an example of a memory controller control sending data to a memory channel (channel 0 and/or 1) that are attached to memory chips 110,)
a memory circuit coupled to the memory controller, (Hily Fig. 2 and [0031] that discloses DRAM chips 110 that are coupled to memory control circuits MMC 118)
wherein the memory circuit includes a plurality of memory portions separately addressable from one another; (Hily [0003] discloses the DRAM is broken into a plurality of memory locations accessed according to a specific memory addresses.)
The remainder of claim 17 recites limitations disclosed in claim 1 above and thus is rejected based on the teaching and rationale of claim 1 above.
Regarding claim 18, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 11 above.
Hily in view of Mutlu and Johnson further teaches wherein the memory controller is further configured to: decode, for a given write command, an address comprising a first plurality of bits and a second plurality of bits, wherein the first plurality of bits of the address indicates a location within the memory circuit in which data associated with the given write command is to be stored, (Hily Abstract, Fig. 3 and [0032]-[0036] discloses write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. Johnson Fig. 1 and [0010]-[0013] teaches that a range of addresses such as address range 112 may be referenced by the physical memory block and the page. Johnson [0079]-[0080] discloses each memory control hardware may manage a range of blocks, and to address a specific address the address includes a module number 806a, block number 806b, and offset 806c, where address ranges are specified by the module number and block number. Thus the address of Hily that specifies the write address will contain a first and middle field (a first code) that is used to match against an address range to determine if the data should be mirrored, and a third field (a second code that is an example of a first plurality of bits) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the first write command).)
and wherein the second plurality bits associated with the first write command indicate whether the data associated with the given write command is to be stored in multiple ones of the plurality of memory portions; (Hily Abstract, Fig. 3 and [0032]-[0036] discloses write request received the system determines if the address of the write request is within a memory address range of one or more address ranges that are to be mirrored. Johnson Fig. 1 and [0010]-[0013] teaches that a range of addresses such as address range 112 may be referenced by the physical memory block and the page. Johnson [0079]-[0080] discloses each memory control hardware may manage a range of blocks, and to address a specific address the address includes a module number 806a, block number 806b, and offset 806c, where address ranges are specified by the module number and block number. Thus the address of Hily that specifies the write address will contain a first and middle field (a first code that is an example of a second plurality of bits that indicate whether the data associated with the given write command is to be stored in multiple memory locations) that is used to match against an address range to determine if the data should be mirrored, and a third field (a second code) that indicates a location within the memory circuit that identifies the page for the write (i.e. indicates a location to write the data associated with the first write command).)
and determine, in response to receiving a read command corresponding to the given write command, based on the second plurality of bits, one or more parameters for reading the data associated with the given write command from the memory circuit. (Hily [0040] discloses that when a read request arrives the system examines the memory read address and directs the read request to the primary read data in the primary memory channel. Thus Hily in view of Mutlu and Johnson reads data associated with the first write command that was previously written, based on the address of the read command and the address of the previously write address which contains a first and middle field (a first code that is an example of a second plurality of bits).
The motivation to combine Johnson into the existing combination is the same as set forth in claim 17 above.
Regarding claim 19, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 18 above.
Hily in view of Mutlu, and Johnson further teaches wherein the one or more parameters for reading the data include a number of the plurality of memory portions from which data associated with the given write command is to be read. (Hily uses the address of a read command to previously written data such as the given write command to determine where the data is to be read from which in turn identifies a set (a number of) of the plurality of memory portions from which the given write command is to be read.)
Regarding claim 21, the combination of Hily, Mutu, and Johnson teaches all of the limitations of claim 17 above. Hily further teaches wherein the memory controller is further configured to, in response to receiving a read command to read the data associated with the first write command, and based on the first value: read the data associated with the first write command from a first one of the plurality of memory portions; (Hily [0040] discloses for a read command the address from the read command is used to read data previously written to the read address (thus associated with the first write command) the data is read from a memory location associated with the primary address (from a first one of the plurality of memory addresses).)
determine a presence of an error in the data associated with the first write command; and in response to determining the presence of the error, read the data associated with the first write command from a second one of the plurality of memory portions (Hily [0045] discloses that if an error is detect on a read command the system will read the data from the secondary location for the address to be read that is associated with the first write command that may be to the same address and the data is read from a second one of the plurality of memory locations associated with the secondary address.)
Claims 2, 5, 7, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hily (Hily et al., US 2023/0176749) and further in view of Mutlu (A publication titled “18-447 Computer Architecture Lecture 21: Main Memory” by Prof Onur Mutlu, Carnegie Mellon University, Spring 015, 3/23/2015) and Johnson (Johnson US 2003/0110205 A1) as detailed in claims 1 and 11 above and further in view of Wang (WANG et al., US 2022/0357891 A1).
Regarding claim 2, the combination of Hily, Mutlu and Johnson teaches all of the limitations of claim 1 above.
Hily in view of Mutlu and Johnson further teaches wherein the memory controller is further configured to, in response to receiving a read command to read the data associated with the first write command, determine whether to, based on the first value, read the data from a particular one of the first or second ranks (Hily [0040] discloses that when a read request arrives the system examines the memory read address and directs the read request to the primary read data in the primary memory channel, and directs the data to the secondary memory channel if an error occurs on the primary channel. Thus Hily in view of Mutlu and Johnson reads data associated with the first write command that was previously written, based on the address of the read command and the address of the previously write address, and reads the data from a particular one of the first rank in the first channel and/or the second rank in the second channel.)
The motivation to combine Mutlu into the existing combination is the same as set forth in claim 1 above.
However the combination does not explicitly disclose depending on estimated respective latencies of reading the data from the first and second ranks.
Wang, of a similar field of endeavor, further discloses depending on estimated respective latencies of reading the data from the first and second ranks. (Wang [Abstract] teaches that the system contains copies of data, a primary copy and a reconstruction copy. Wang [0120] discloses the storage resources may be DRAM. Wang [0281] discloses the system identifies a second timeout that represents a period of time after which an error condition is believed to have occurred reading the primary copy of the data. Thus associates errors with a latency period, and selects data from the mirrored copy (the second rank) if the first rank exhibits errors (reaches a second timeout value) and thus is expected to have a greater latency than reading the data from the mirrored copy.)
Hily, Mutlu, Johnson, and Wang are in a similar field of endeavor as all relate to managing data in RAMs. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate reading data from a mirrored copy of the data if the first data is assumed to be invalid as taught by Wang in a solution that mirrors data as taught by Hily, Mutlu and Johnson, thus combining prior art elements according to known methods to yield predictable results (to save read resources by reading only one copy of the data that is expected to be valid and will produce the lowest latency read cycle.)
Regarding claim 5, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 4 above. However, the combination does not explicitly teach wherein, to determine the presence of the error, the memory controller is configured to compare a checksum of the data associated with the first write command to a known checksum value. .
Wang, of a similar field of endeavor, further teaches wherein, to determine the presence of the error, the memory controller is configured to compare a checksum of the data associated with the first write command to a known checksum value. (Wang [0128] teaches that when reading data from a mirrored solution, the system may maintain checksums and verify the data to be read using the checksums.)
Hily, Mutlu, Johnson, and Wang are in a similar field of endeavor as all relate to managing data in DRAM. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate performing data verification using a stored ECC as taught by Wang in a solution that mirrors data and verifies the data written using an ECC as taught by Hily, Mutlu, and Johnson, thus combining prior art elements according to known methods to yield predictable results (to implement the ECC verification check identified by Hily using the well-known technique disclosed by Wang for ECC verification).)
Regarding claim 7, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 1 above. However, the combination does not explicitly teach wherein the memory controller is further configured to: receive metadata associated with the first write command; and perform error checking, using the metadata, on a subsequent read of the data associated with the first write command.
Wang, of a similar field of endeavor, further teaches wherein the memory controller is further configured to: receive metadata associated with the first write command; and perform error checking, using the metadata, on a subsequent read of the data associated with the first write command. (Wang [0056] discloses that the system may maintain metadata for the data written, including information that a particular memory block has failed. Thus the solution of Hily, Mutlu, Johnson, and Wang reads data, it will read the metadata data associated with the data to read to determine if the data written is known to contain an error. )
Hily, Mutlu, Johnson, and Wang are in a similar field of endeavor as all relate to managing data in RAM. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate reading metadata associated with mirrored data as taught by Wang into the solution of Hily, Mutlu, and Johnson that maintains mirrored data, thus combining prior art elements according to known methods to yield predictable results (to use the actual history of the data that is to be read as taught by Wang to have a more accurate picture of if the data is valid or not.).
Regarding claim 14, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 13 above.
The remainder of claim 14 recites limitations in claim 2 above and thus is rejected based on the teaching and rationale of claim 2 above.
Regarding claim 20, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 18 above. However, the combination does not explicitly teach wherein the one or more parameters for reading the data include which, based on an estimated read latency, of the plurality of memory portions from which data associated with the given write command is to be read.
Wang, of a similar field of endeavor, further teaches wherein the one or more parameters for reading the data include which, based on an estimated read latency, of the plurality of memory portions from which data associated with the given write command is to be read. (Hily [0032]-[0036] and [0040\ discloses that the system may determine if it should read the primary data based on the address of the data, which is an example of one or more parameters for reading the data. Wang [Abstract] teaches that the system contains copies of data, a primary copy and a reconstruction copy. Wang [0120] discloses the storage resources may be DRAM. Wang [0281] discloses the system identifies a second timeout that represents a period of time after which an error condition is believed to have occurred reading the primary copy of the data. Thus associates errors with a latency period, and selects data from the mirrored copy (the second rank) if the first rank exhibits errors (reaches a second timeout value) and thus is expected to have a greater latency than reading the data from the mirrored copy. The detection of the error is based on the address, thus the one or more parameters is combined with the address error history to estimate read latency for the plurality of memory portions from which data associated with the given write command is to be read.)
Hily, Mutlu, Johnson and Wang are in a similar field of endeavor as all relate to managing data in RAM. Thus it would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate reading data from a mirrored copy of the data if the first data is assumed to be invalid and thus has a high latency as taught by Wang in a solution that mirrors data as taught by Hily, Mutlu, and Johnson thus combining prior art elements according to known methods to yield predictable results (to save read resources by reading only one copy of the data that is expected to be valid and will produce the lowest latency read cycle.)
Claims 3 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Hily (Hily et al., US 2023/0176749) and further in view of Mutlu (A publication titled “18-447 Computer Architecture Lecture 21: Main Memory” by Prof Onur Mutlu, Carnegie Mellon University, Spring 015, 3/23/2015) and Johnson (Johnson US 20030110205 A1) as detailed in claims 1 and 11 above and further in view Shaw’177 (Shaw US 2006/0288177 A1)
Regarding claim 3, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 1 above. However, the combination does not explicitly teach wherein the memory controller is further configured to, in response to receiving a read command to read the data associated with the first write command, and based determining the first code has the first value: read the data associated with the first write command from the first rank and the second rank; and compare the data associated with the first write command as read from the first rank to the data associated with the first write command as read from the second rank.
Shaw’177, of a similar field of endeavor, further teaches wherein the memory controller is further configured to, in response to receiving a read command to read the data associated with the first write command, and based determining the first code has the first value: read the data associated with the first write command from the first rank and the second rank; and compare the data associated with the first write command as read from the first rank to the data associated with the first write command as read from the second rank. (Shaw’177 [0015]-[0016] discloses that when mirrored data is to be read by the host CPU, the system may perform a comparison of the primary data and the mirrored (copied) data. Thus the solution of Hily, Mutlu, Johnson, and Shaw’177 would identify the rank of the data to read based on the logical address in the read command that is translated to a physical address including a rank, determine it was to a mirrored rank such as rank 1, and read data from rank 1 and 2 and perform a comparison of the data from both ranks, including the first and middle fields as identified by Johnson (the first code).).
Hily, Mutlu, Johnson, and Shaw’177 are all in a similar field of endeavor as all relate to processing RAM including DRAM memory that includes DDR4 memory. Thus it would have been obvious to a person of ordinary skill in the arts before the effectively filed date of the claimed invention to incorporate the comparison as taught by Shaw’177 into the solution of Hily, Mutlu, and Johnson that mirrors data to provide a means to reduce errors returned to a host. Thus combining prior art elements according to known methods to yield predictable results (reducing the errors returned to the host by insuring that the two read results are identical before returning data read to a host given DRAM memory is known to suffer from flipped bits and errors).)
Regarding claim 15, the combination of Hily, Mutlu, and Johnson teaches all of the limitations of claim 13 above. However, the combination does not explicitly teach further comprising: reading the data associated with the first write command from the first rank and from the second rank; and performing a comparison of the data associated with the first write command as read from the first rank and the second rank to determine a presence of an error.
Shaw’177, of a similar field further teaches further comprising: reading the data associated with the first write command from the first rank and from the second rank; and performing a comparison of the data associated with the first write command as read from the first rank and the second rank to determine a presence of an error. (Shaw’177 [0015]-[0016] discloses that when mirrored data is to be read by the host CPU, the system may perform a comparison of the primary data and the mirrored (copied) data. Thus the solution of Hily, Mutlu, Johnson, and Shaw’177 would identify the rank of the data to read based on the physical address in the read command (including the rank address), determine it was to a mirrored rank such as rank 1, and read data from rank 1 and 2 and perform a comparison of the data from both ranks.).
Hily Mutlu, Johnson, and Shaw’177 are all in a similar field of endeavor as all relate to processing RAM memory, including DRAM (a form of RAM) memory which includes DDR4 memory (a form of DRAM memory). Thus it would have been obvious to a person of ordinary skill in the arts before the effectively filed date of the claimed invention to incorporate the comparison as taught by Shaw’177 into the solution of Hily, Mutlu, and Johnson that mirrors data to provide a means to reduce errors returned to a host. Thus combining prior art elements according to known methods to yield predictable results (reducing the errors returned to the host by insuring that the two read results are identical before returning data read to a host given DRAM memory is known to suffer from flipped bits and errors.)
Response to Remarks
Examiner thanks applicant for their claim amendments and remarks of5/18/2026. They have been fully considered.
Applicant argues on page 10 of their remarks that Hily in view of Mutlu does not teach or suggest the amended limitations.
Examiner agrees. Therefore, the rejection has been withdrawn. However, upon further consideration and in response to the claims as amended a new ground(s) of rejection is made in based on Hily in view of Mutlu and Johnson (Johnson US 2003/0110205 A1) as detailed in the rejections above.
Applicant argues on page 11 of their remarks “Hily in view of Mutlu does not teach or suggest determining whether to mirror data on the basis of ranks”… More generally, neither Mutlu nor Hily provide any teaching or suggestion that would lead one of ordinary skill in the art to perform mirroring on the basis of a portion of the memory hierarchy that is lower than the channel level.
Examiner respectfully disagrees. As noted by the office action of 4/8/2026 and by applicants remarks A DRAM system is organized as follows:
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and further notes “See also Mutlu pages 78 and 74 that a single memory channel may be compose of a single DIMM, that contains a first rank on the front of the DIMM and a second rank on the back of a DIMM.”
As noted in the office action and as detailed above, each channel is made up of separate and distinct DIMMs, which are made up of separate and distinct ranks, which are made up of separate and distinct chips, which are made up of separate and distinct banks, which are make up a separate and distinct row/column array of memory cells. As is known by a POSITA, one does not write to a channel where the write stops at the channel in the hierarchy as suggested by Applicants remarks. The target of the write is always the cells identified in the write command. When one issues a write to a channel, it identifies the appropriate DIMM, Rank, Chip, Bank, Row/Column array, and cells for the write and write to the appropriate DIMM, Rank, Chip, Bank, Row/Column array, and cells and writes to the cells.
Furthermore, applicant is arguing a limitation not claimed. The claims do not recite “perform mirroring on the basis of a portion of the memory hierarchy that is lower than the channel level”. The claims merely recite writing to a first rank and a second rank, or to a single one of first and second rank. When Hily is writing to separate channels, it is writing to separate ranks as claimed.
Applicant argues on page 12 of their remarks “II. The Proposed Combination would Change Hily's Principle of Operation and Render it Unsatisfactory for Its Intended Purpose:
… Hily's disclosed mirroring architecture is expressly channel-based. Paragraph [0033] of Hily explains that the write request is communicated over a first memory channel selected based on the write memory address. Paragraph [0034] then explains that, if the write memory address is within a mirrored address range stored in the mirror address range registers, the memory mirror agent communicates the write data to a second memory channel that was not assigned as the primary memory channel for the write request. Paragraph [0035] further explains that Hily may communicate the write data to that second memory channel using a new calculated memory address that maps to a secondary memory channel address. Paragraph [0036] likewise continues to describe Hily's operation in terms of primary and redundant memory channels. Hily's disclosed mirroring mechanism is therefore not an incidental use of channels, but on the contrary is the principle under which Hily is designed to operate.”
Applicant argues the combination changes Hily’s principle and renders it unsatisfactory because Hily’s mirroring Architecture is expressly channel-based and “Hily’s disclosed mirroring mechanism is therefore not an incidental use of channels, but on the contrary is the principle under which Hily is designed to operate”.
Examiner respectfully disagrees. As noted by the office action of 4/8/2026 and by applicants remarks A DRAM system is organized as follows:
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and further notes “See also Mutlu pages 78 and 74 that a single memory channel may be compose of a single DIMM, that contains a first rank on the front of the DIMM and a second rank on the back of a DIMM.”
For DRAM memory, each channel is made up of DIMMs, which are made up of ranks, which are made up of chips, which are made up of banks, which are make up a row/column array of memory cells. As is known by a POSITA, one does not write to a channel where the write stops at the channel in the hierarchy as suggested by Applicants remarks. The target of the write is always the separate and distinct cells identified in the write command. When one issues a write to a channel, it identifies the appropriate DIMM, Rank, Chip, Bank, Row/Column array, and cells for the write and write to the appropriate DIMM, Rank, Chip, Bank, Row/Column array, and cells.
Mutlu’s description of how DRAM memory is organized does not negate the organization of Hily, it merely explains how the DRAM of Hily is organized, including how it’s channels are made up of DIMMs, that are made up of ranks, etc.. and that by writing to separate channels one is writing to separate ranks as claimed.
Johnson teaches managing addresses in a memory system that directs request to separate memory devices having separate controllers (see Johnson [0079]-[0081]) using a virtual memory system. As detailed in the rejection above, Johnson teaches that the address field may be broken down into two segments, a first segment identifying a range of addresses, and the second segment identifying an offset within the address. Thus the range of addresses for a given controller as specified by Hily may be implemented using the first segment (i.e. code) of Johnson. The virtual system of Johnson performs logical to physical address translation using the first segment/code and appends the second code as an offset within the newly identified physical address. Thus saves significant translation address space, reducing the address translation table to 1/(second code) of the original size without this enhancement. Thus the solution of Hily in view of Mutsu and Johnson would route requests to separate ranks within separate controllers using the first segment/code to save space in a memory mapping table to support virtual addressing where the Application addresses memory using a logical address the operating system maintains a mapping to the physical location of the data. Enabling the operating system to perform routine duties such as performing error detection and correction that often involves moving data to new locations when the original location is known to be defective hardware. Furthermore, Johnson provides a means of memory mapping that enable a system to remap a range of physical memory addresses from one machine (hardware) memory resource to another without requiring the server to be rebooted. Thus providing hardware recovery without the delay expense associated with rebooting a server. The combination of Hily in view of Mutlu and Johnson does not render the solution of Hily as unsatisfactory for its intended purpose. It enhances Hily as enabling it to function in a system that provides virtual addressing to applications while enabling the operating system to perform error detection/correction as needed with improved error correction efficiency.
Applicant argues on page 13 of their remarks “The Office Action, however, proposes to modify Hily with Mutlu such that the mirroring is performed on a portion of a memory hierarchy, ranks, that are lower than and distinct from channels.”
Examiner respectfully disagrees. As detailed above, the rejection notes that when mirroring data to a portion of the memory hierarchy such as to one or more a memory controllers, it is mirroring data to one or more memory ranks as claimed. Mirroring to two ranks is a byproduct of mirroring to two channels. This does not require replacing Hily’s disclosed channel-to-channel mirroring with a different architecture and does not require dispensing with Hily’s use of a second memory channel, and in at least some embodiments, a new calculated secondary-channel address as Applicant argues.
The proposed combination preserve and enhance Hily’s principle of operation.
Applicant further argues on page 13 of their remarks “Not only would the proposed combination change Hily's principle of operation, it would also render it unsatisfactory for its intended purpose. Paragraph [0007] of Hily states, in pertinent part: In this regard, the MCU includes dedicated memory channels to the dedicated memory controllers that would be accessible to the memory mirror agent. Traffic associated with memory mirroring would not have to be placed on a system bus and/or in the computer system network that could otherwise decrease efficiency and increase network traffic/bandwidth. Thus, the memory mirror agent can be interfaced between an external interface to the MCU and these dedicated memory channels to directly control the memory channels of the MCU. (Emphasis added).
Thus, as outlined above by Hily, the mirroring-by-channel arrangement is provided for the purposes of efficiency and reducing network traffic/bandwidth. By modifying Hily to performing mirroring at a lower portion of the memory hierarchy (i.e. within a single channel), the desired effects of increased efficiency and reduced network traffic/bandwidth would be lost.”
Examiner respectfully disagrees. As noted above, Hily in view of Mutlu discloses directing writes to either two separate channels, or to a single channel based on a write address compared to address ranges. Johnson further discloses that data directed to channels that manage address space for separate address ranges may be use a portion of the address space to identify the location of the data (both the target and the address ranges) save space in a solution that implements logical to physical address translation. The network traffic/bandwidth efficiencies will be maintained.
Applicant further argues on page 14 of their remarks “In the portion of Hily quoted above, the advantages of flexibility that arise from the stated principle of operation id discussed, along with the ability to obtain a copy of data from one channel if another channel incurs a fault. However, the proposed modification would move the mirroring operation down in the memory hierarchy to the rank level and within a single channel. Accordingly, the desired flexibility and ability to recover data in the event of a channel fault would be lost by the proposed modification.”
Examiner respectfully disagrees. The proposed modification does not move the mirroring operation down in the memory hierarchy to the rank level within a single channel. Instead the proposed prior art simply notes that by routing write requests to separate channels it is routing the requests to separate ranks. No flexibility to recover data in the event of a channel fault would occur and the proposed solution does not change the principle of operation of Hily and does not render Hily unsatisfactory for its intended purpose.
Conclusion
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/JANICE M. GIROUARD/Primary Examiner, Art Unit 2138
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