DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim 2 is cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 6-12, 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al (US Pub 2021/0201816) in view of Park et al (US Pub 2017/0206847).
With respect to claim 1, KIM discloses a display device (par 0002; discloses present disclosure relates to a gate driving circuit and a display apparatus comprising the same) comprising: a display panel in which a plurality of subpixels is disposed (fig. 1; discloses display panel 100 comprising plurality of unit pixels; par 0051; discloses each of the plurality of unit pixels UP according to one embodiment may include first to fourth subpixels P1, P2, P3 and P4); and a gate driving circuit configured to output gate signals to the plurality of subpixels, (fig. 1; gate driving circuit portion 500; par 0090; discloses the gate driving circuit portion 500 may generate scan signals respectively corresponding to the image display period IDP, the black display period BDP and the sensing period RSP based on the gate control signal GCS supplied from the timing controller 300, and may supply the generated scan signals to the corresponding gate line) wherein the gate driving circuit comprises: a gate signal generation circuit configured to generate the gate signals (fig. 10; discloses internal configuration of the nth stage shift register where components SCC1, NCC1, IC1 and NRC1 form the gate signal generator that control and generate the voltage at the node 1Qo; see par 0215; discloses the first node control circuit NCC1 may be embodied to control the potential of the first odd control node 1Qo through the first gate high potential voltage GVdd1 in response to the (n−3)th carry signal CS[n−3] (first front carry signal)); a gate signal output circuit configured to output the gate signals (fig. 10; discloses each stage of the shift register includes a output buffer circuit OBC1; par 0219; discloses the first output buffer circuit OBC1 may be embodied to output the nth to (n+3)th scan shift clocks SCLK[n] to SCLK[n+3] as nth to (n+3)th scan signals SC[n] to SC[n+3] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo and 1Qbe);
KIM discloses a timing controller configured to generate a plurality of scan clock signals for controlling output timings of the gate signals (par 0159; discloses the gate control signal line GCSL receives the gate control signal GCS supplied from the timing controller 300. The gate control signal line GCSL according to one embodiment may include a gate start signal line, a first reset signal line, a second reset signal line, a plurality of gate driving clock lines; par 0165; discloses The plurality of gate driving clock lines may include a plurality of carry shift clock lines which receives a plurality of carry shift clocks, and a plurality of scan shift clock lines which receives a plurality of scan shift clocks. The clock lines included in the plurality of gate driving clock lines may selectively be connected to the front dummy stage circuit portion DSTP1, the first to mth stage circuits ST[1] to ST[m], and the rear dummy stage circuit portion DSTP2);
KIM doesn’t expressly disclose a clock decoder configured to generate a plurality of scan clock signals for controlling output timings of the gate signals based on at least two clock signals; wherein the at least two clock signals comprise a first clock signal and a second clock signal, and wherein the clock decoder is configured to output the first clock signal as a scan clock signal, among the plurality of scan clock signals, according to an output timing that is controlled by the second clock signal;
In the same field of endeavor, Park discloses a display device comprising clock generation circuit (see abstract); Park discloses a clock decoder configured to generate a plurality of scan clock signals for controlling output timings of the gate signals based on at least two clock signals (fig. 2; discloses clock generation circuit 320 outputs plurality of clock signals based on CPV1-CPV4); wherein the at least two clock signals comprise a first clock signal and a second clock signal, (fig. 7; switching unit 430 of the clock generation circuit 320 receives a first clock signal CPV1 and second clock signal SW1) and wherein the clock decoder is configured to output the first clock signal as a scan clock signal, among the plurality of scan clock signals, according to an output timing that is controlled by the second clock signal (par 0092; discloses the switching unit 430 includes switching transistors STR1 to STR8. The switching transistors STR1 to STR8 correspond to the gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4, respectively. Also, the switching transistors STR1 to STR8 correspond to the switching signals SW1 to SW8, respectively; par 0093; discloses the switching transistors STR1 and STR2 output the gate pulse signal CPV1 as the gate clock signals CKV1 and CKVB1, in response to the corresponding switching signals SW1 and SW2);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by KIM to use the clock generation circuit disclosed by Park in the display device in order to prevent the display device from any damage caused due to over-current flow from the current generation circuit by including an over-current protection function built into the clock generation circuit.
With respect to claim 3, KIM as modified by Park further discloses wherein the clock decoder (Park; fig. 2; clock generation circuit 320) comprises a switch interposed between a line through which the first clock signal is input and a scan clock signal line to control on/off of output of the first clock signal according to the second clock signal; (Park; fig. 6; switching unit 430; par 0087; discloses the switching unit 430 outputs the gate pulse signals CPV1 to CPV4 as the gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 in response to switching signals SW1 to SW8 transmitted from the over-current protecting unit 440; par 0093; discloses the switching transistors STR1 and STR2 output the gate pulse signal CPV1 as the gate clock signals CKV1 and CKVB1, in response to the corresponding switching signals SW1 and SW2; par 0103; discloses when the switching signal SW1 has a low level, the switching transistor STR1 of FIG. 7 is turned off to allow the gate clock signal CKV1 to be maintained or substantially maintained at the ground voltage GND. When the switching signal SW2 has a high level, the switching transistor STR2 of FIG. 7 is turned on to allow the gate pulse signal CPV1 that is swung between a high voltage CPVH and the ground voltage GND to be outputted as the gate clock signal CKVB1.);
With respect to claim 4, KIM as modified by Park further discloses wherein the clock decoder comprises: a transistor having a first electrode connected to the line through which the first clock signal is input; a gate electrode connected to a line through which the second clock signal is input; and a second electrode connected to a line through which the scan clock signals are applied to the gate signal output unit; (Park; fig. 7; discloses switching unit 430 within the clock generation circuit 320 that includes a transistor SRT1 having first electrode connected to clock line CPV1 and gate electrode connected to control signal SW1 and second electrode generating the output clock signal CKV1);
With respect to claim 6, KIM as modified by Park further discloses wherein the clock decoder generates n×m scan clock signals on the basis of n first clock signals and m second clock signals, n and m being positive integers greater than 1 (Park; par 0086; discloses The clock generation unit 420 inverts the gate pulse signals CPV1 to CPV4 transmitted from the timing controller 310 of FIG. 2 into gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4. For example, the clock generation unit 420 outputs a pair of complementary gate clock signals CKV1 and CKVB1 on the basis of the gate pulse signal CPV1. The clock generation unit 420 outputs a pair of complementary gate clock signals CKV2 and CKVB2 on the basis of the gate pulse signal CPV2. The clock generation unit 420 outputs a pair of complementary gate clock signals CKV3 and CKVB3 on the basis of the gate pulse signal CPV3. The clock generation unit 420 outputs a pair of complementary gate clock signals CKV4 and CKVB4 on the basis of the gate pulse signal CPV4. The gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 may be signals that are swung between the gate on voltage VON and the gate off voltage VOFF. The gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 may be set to have phases that are different from each other during one period.);
With respect to claim 7, KIM as modified by Park discloses wherein the gate signal output circuit comprises: a pull-up transistor controlled by a voltage level of a Q node (KIM; fig. 11; transistor T29; see par 0305; discloses the 29th TFT T29 (or first odd pull-up TFT) may output the nth scan signal SC[n] having a scan pulse of a high voltage corresponding to the nth scan shift clock SCLK[n] to the first output node No1 in accordance with the voltage of the first odd control node 1Qo to supply the scan pulse of the nth scan signal SC[n] to the nth gate line ); and a pull-down transistor controlled by a voltage level of a QB node, (KIM; fig. 11; transistor T30; see par 0306; discloses may output the nth scan signal SC[n] of a low voltage corresponding to the first gate low potential voltage GVss1 to the first output node No1 in accordance with the voltage of the second odd control node 1Qbo to supply the nth scan signal SC[n] of the low voltage to the nth gate line.) wherein first to k-th gate signals having the voltage level of the Q node or the voltage level of the QB node are output in accordance with the scan clock signals, k being a positive integer greater than 1 (KIM; par 0219; discloses The first output buffer circuit OBC1 may be embodied to output the nth to (n+3)th scan shift clocks SCLK[n] to SCLK[n+3] as nth to (n+3)th scan signals SC[n] to SC[n+3] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo and 1Qbe. The first output buffer circuit OBC1 may be embodied to output the nth carry shift clock CCLK[n] as the nth carry signal CS[n] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo and 1Qbe).
With respect to claim 8, KIM as modified by Park discloses wherein the gate signal output circuit sequentially outputs the first to k-th gate signals on the basis of the scan clock signals when the voltage level of the Q node is a high voltage level (KIM; par 0379; discloses For the third display period td3 of the image display period IDP, as the nth to (n+)th scan shift clocks SCLK[n] to SCLK[n+3] and the nth carry shift clock CCLK[n] are sequentially input as the high voltages, bootstrapping is generated in the first odd control node 1Qo, whereby each of the odd pull-up TFTs T29, T32, T35, T38 and T41 of the first output buffer circuit OBC1 is completely turned on).
With respect to claim 9, KIM as modified by Park discloses wherein the scan clock signals are input to a drain electrode of the pull-up transistor (KIM; par 0305; discloses the 29th TFT T29 may include a gate electrode connected to the first odd control node 1Qo, a first source/drain electrode connected to the first output node No1 (or scan output terminal), and a second source/drain electrode connected to the nth scan shift clock line).
With respect to claim 10, KIM as modified by Park discloses wherein the gate signal output circuit further comprises a boosting capacitor connected between a gate and a source of the pull-up transistor (KIM; fig. 11; capacitor Cc1; par 0310; discloses The first coupling capacitor Cc1 may be embodied between the first odd control node 1Qo and the first output node No1. The first coupling capacitor Cc1 may generates bootstrapping in the first odd control node 1Qo in accordance with phase shift (or change) of the nth scan shift clock SCLK[n], whereby the 29th TFT T29 may completely turned on. As a result, the nth scan shift clock SCLK[n] of the high voltage may be output to the first output node No1 through the 29th TFT T29, which is completely turned, without loss).
With respect to claim 11, KIM discloses a gate driving circuit (fig. 1; gate driving circuit portion 500;) comprising: a pull-up transistor controlled by a voltage level of a Q node (fig. 11; transistor T29; see par 0305; discloses the 29th TFT T29 (or first odd pull-up TFT) may output the nth scan signal SC[n] having a scan pulse of a high voltage corresponding to the nth scan shift clock SCLK[n] to the first output node No1 in accordance with the voltage of the first odd control node 1Qo to supply the scan pulse of the nth scan signal SC[n] to the nth gate line ); a pull-down transistor controlled by a voltage level of a QB node (fig. 11; transistor T30; see par 0306; discloses may output the nth scan signal SC[n] of a low voltage corresponding to the first gate low potential voltage GVss1 to the first output node No1 in accordance with the voltage of the second odd control node 1Qbo to supply the nth scan signal SC[n] of the low voltage to the nth gate line); and wherein first to k-th gate signals having the voltage level of the Q node or the voltage level of the QB node are output in accordance with the scan clock signals, k being a positive integer greater than 1 (par 0219; discloses The first output buffer circuit OBC1 may be embodied to output the nth to (n+3)th scan shift clocks SCLK[n] to SCLK[n+3] as nth to (n+3)th scan signals SC[n] to SC[n+3] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo and 1Qbe. The first output buffer circuit OBC1 may be embodied to output the nth carry shift clock CCLK[n] as the nth carry signal CS[n] in response to the voltage of each of the first to third odd control nodes 1Qo, 1Qbo and 1Qbe);
KIM discloses a timing controller configured to generate a plurality of scan clock signals for controlling output timings of the gate signals (par 0159; discloses the gate control signal line GCSL receives the gate control signal GCS supplied from the timing controller 300. The gate control signal line GCSL according to one embodiment may include a gate start signal line, a first reset signal line, a second reset signal line, a plurality of gate driving clock lines; par 0165; discloses the plurality of gate driving clock lines may include a plurality of carry shift clock lines which receives a plurality of carry shift clocks, and a plurality of scan shift clock lines which receives a plurality of scan shift clocks. The clock lines included in the plurality of gate driving clock lines may selectively be connected to the front dummy stage circuit portion DSTP1, the first to mth stage circuits ST[1] to ST[m], and the rear dummy stage circuit portion DSTP2);
KIM doesn’t expressly disclose a clock decoder configured to generate a plurality of scan clock signals for controlling output timings of the gate signals based on at least two clock signals; wherein the at least two clock signals comprise a first clock signal and a second clock signal, and wherein the clock decoder is configured to output the first clock signal as a scan clock signal, among the plurality of scan clock signals, according to an output timing that is controlled by the second clock signal;
In the same field of endeavor, Park discloses a display device comprising clock generation circuit (see abstract); Park discloses a clock decoder configured to generate a plurality of scan clock signals for controlling output timings of the gate signals based on at least two clock signals (fig. 2; discloses clock generation circuit 320 outputs plurality of clock signals based on CPV1-CPV4); wherein the at least two clock signals comprise a first clock signal and a second clock signal, (fig. 7; switching unit 430 of the clock generation circuit 320 receives a first clock signal CPV1 and second clock signal SW1) and wherein the clock decoder is configured to output the first clock signal as a scan clock signal, among the plurality of scan clock signals, according to an output timing that is controlled by the second clock signal (par 0092; discloses the switching unit 430 includes switching transistors STR1 to STR8. The switching transistors STR1 to STR8 correspond to the gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4, respectively. Also, the switching transistors STR1 to STR8 correspond to the switching signals SW1 to SW8, respectively; par 0093; discloses the switching transistors STR1 and STR2 output the gate pulse signal CPV1 as the gate clock signals CKV1 and CKVB1, in response to the corresponding switching signals SW1 and SW2);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by KIM to use the clock generation circuit disclosed by Park in the display device in order to prevent the display device from any damage caused due to over-current flow from the current generation circuit by including an over-current protection function built into the clock generation circuit.
With respect to claim 12, KIM as modified by SUNG discloses the scan clock signals are applied to a gate signal output unit comprising the pull-up and pull-down transistors (KIM; fig. 11; discloses clock signal SCLKn is applied to the pull-up transistor T29 and pull-down transistor T30); Park discloses wherein the clock decoder (Park; fig. 2; clock generation circuit 320); comprises a transistor having a first electrode connected to a first clock signal input line, a gate electrode connected to a second clock signal input line, and a second electrode connected to a line through which the scan clock signals are applied (Park; fig. 7; discloses switching unit 430 within the clock generation circuit 320 that includes a transistor SRT1 having first electrode connected to clock line CPV1 and gate electrode connected to control signal SW1 and second electrode generating the output clock signal CKV1);
With respect to claim 14, KIM as modified by Park discloses wherein the clock decoder generates n×m scan clock signals on the basis of n first clock signals and m second clock signals, n and m being positive integers greater than 1 (par 0086; discloses The clock generation unit 420 inverts the gate pulse signals CPV1 to CPV4 transmitted from the timing controller 310 of FIG. 2 into gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4. For example, the clock generation unit 420 outputs a pair of complementary gate clock signals CKV1 and CKVB1 on the basis of the gate pulse signal CPV1. The clock generation unit 420 outputs a pair of complementary gate clock signals CKV2 and CKVB2 on the basis of the gate pulse signal CPV2. The clock generation unit 420 outputs a pair of complementary gate clock signals CKV3 and CKVB3 on the basis of the gate pulse signal CPV3. The clock generation unit 420 outputs a pair of complementary gate clock signals CKV4 and CKVB4 on the basis of the gate pulse signal CPV4. The gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 may be signals that are swung between the gate on voltage VON and the gate off voltage VOFF. The gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 may be set to have phases that are different from each other during one period.);
With respect to claim 15, KIM as modified by Park discloses further comprising a boosting capacitor connected between a gate and a source of the pull-up transistor (KIM; fig. 11; capacitor Cc1; par 0310; discloses the first coupling capacitor Cc1 may be embodied between the first odd control node 1Qo and the first output node No1. The first coupling capacitor Cc1 may generates bootstrapping in the first odd control node 1Qo in accordance with phase shift (or change) of the nth scan shift clock SCLK[n], whereby the 29th TFT T29 may completely turned on. As a result, the nth scan shift clock SCLK[n] of the high voltage may be output to the first output node No1 through the 29th TFT T29, which is completely turned, without loss).
With respect to claim 16, KIM as modified by Park discloses wherein the first clock signal and the second clock signal have different pulse periodicities (Park; par 0103; discloses when the switching signal SW1 has a low level, the switching transistor STR1 of FIG. 7 is turned off to allow the gate clock signal CKV1 to be maintained or substantially maintained at the ground voltage GND. When the switching signal SW2 has a high level, the switching transistor STR2 of FIG. 7 is turned on to allow the gate pulse signal CPV1 that is swung between a high voltage CPVH and the ground voltage GND to be outputted as the gate clock signal CKVB1; fig. 9; discloses an example where SW2 is high for a period that is equal to plurality of periods of the clock signal CKVB1; hence their pulse periodicities are different).
With respect to claim 17, KIM as modified by Park discloses wherein the first clock signal and the second clock signal have different pulse periodicities (Park; par 0103; discloses when the switching signal SW1 has a low level, the switching transistor STR1 of FIG. 7 is turned off to allow the gate clock signal CKV1 to be maintained or substantially maintained at the ground voltage GND. When the switching signal SW2 has a high level, the switching transistor STR2 of FIG. 7 is turned on to allow the gate pulse signal CPV1 that is swung between a high voltage CPVH and the ground voltage GND to be outputted as the gate clock signal CKVB1; fig. 9; discloses an example where SW2 is high for a period that is equal to plurality of periods of the clock signal CKVB1; hence their pulse periodicities are different).
With respect to claim 18, KIM as modified by Park discloses wherein the first clock signal has a same pulse width as the scan clock signal generated by the clock decoder (Park; par 0087; discloses The switching unit 430 outputs the gate pulse signals CPV1 to CPV4 as the gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 in response to switching signals SW1 to SW8 transmitted from the over-current protecting unit 440; i.e. the pulse width of the output clock signal is same as the input clock signal).
With respect to claim 19, KIM as modified by Park discloses wherein the first clock signal has a same pulse width as the scan clock signal generated by the clock decoder (Park; par 0087; discloses The switching unit 430 outputs the gate pulse signals CPV1 to CPV4 as the gate clock signals CKV1, CKVB1, CKV2, CKVB2, CKV3, CKVB3, CKV4, and CKVB4 in response to switching signals SW1 to SW8 transmitted from the over-current protecting unit 440; i.e. the pulse width of the output clock signal is same as the input clock signal).
Claim(s) 5, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al (US Pub 2021/0201816) in view of Park et al (US Pub 2017/0206847) and IWASE et al (US Pub 2021/0327388).
With respect to claim 5, KIM as modified by Park don’t expressly disclose further comprising a boosting capacitor connected between the gate electrode and the second electrode;
In the same field of endeavor, IWASE disclose display device comprising a output circuit comprising a boosting capacitor connected between the gate electrode and the second electrode (par 0088; discloses the boost capacitor C1, one end is connected to the gate terminal of the thin film transistor T1, and another end is connected to the source terminal of the thin film transistor T1; par 0101; discloses the voltage change of the gate bus line GL(n) (that is, the voltage change of the scanning signal G(n)) pushes up the voltage of the first state node N1(n) via the boost capacitor C1. By such a boost operation, a voltage sufficiently higher than the normal high level is applied to the gate terminal of the thin film transistor T1. As a result, the thin film transistor T1 is at the completely on state, and the gate bus line GL(n) on the nth line is charged to the completely high level from the one end side (left side in FIG. 1));
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by KIM as modified by Park to incorporate the teachings of IWASE to include a capacitor connected between the gate electrode and source electrode of the output transistor in order to improve the output signal of the output circuit by boosting the voltage at the gate electrode.
With respect to claim 13, KIM as modified by Park don’t expressly disclose further comprising a boosting capacitor connected between the gate electrode and the second electrode;
In the same field of endeavor, IWASE disclose display device comprising a output circuit comprising a boosting capacitor connected between the gate electrode and the second electrode (par 0088; discloses the boost capacitor C1, one end is connected to the gate terminal of the thin film transistor T1, and another end is connected to the source terminal of the thin film transistor T1; par 0101; discloses the voltage change of the gate bus line GL(n) (that is, the voltage change of the scanning signal G(n)) pushes up the voltage of the first state node N1(n) via the boost capacitor C1. By such a boost operation, a voltage sufficiently higher than the normal high level is applied to the gate terminal of the thin film transistor T1. As a result, the thin film transistor T1 is at the completely on state, and the gate bus line GL(n) on the nth line is charged to the completely high level from the one end side (left side in FIG. 1));
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by KIM as modified by Park to incorporate the teachings of IWASE to include a capacitor connected between the gate electrode and source electrode of the output transistor in order to improve the output signal of the output circuit by boosting the voltage at the gate electrode.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 11 have been considered but are moot because the arguments do not apply to the new reference being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUJIT SHAH/Examiner, Art Unit 2624