Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-17, and 19-22 are present for examination.
Response to Amendment
Applicant’s arguments with respect to the rejection(s) of claim(s) 1, 3-17, and 19-20 under 35 U.S.C. §102(a)(1) and 35 U.S.C. §103 have been fully considered and are persuasive. However, upon further consideration, Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Applicants’ arguments are rendered moot in view of the present Office Action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20070242513 A1) in view of Greene et al. (US 20190172522 A1).
Regarding claim 1: Chang discloses an improved static random access (SRAM) cell (30, FIG. 3D): comprising: a word write line (write word line WWL, FIG. 3D);a first bit line (bit line BLN, FIG. 3D); a first storage node (storage node S2, FIG. 3D); a second storage node (storage node S1, FIG. 3D); a first voltage rail (node shared by transistors P1 and P2, FIG. 3D), a second voltage rail (ground shared by transistors N1 and N2, FIG. 3D); a first passgate transistor (pass transistor N4, FIG. 3D) including a gate terminal, a source terminal, and a drain terminal (FIG. 3D), said gate terminal of the first passgate transistor being electrically connected to the word write line (gate of pass transistor N4 connected to word write line WWL, FIG. 3D), source terminal being electrically connected to the first bit line (source of pass transistor N4 connected to bit line BLN, FIG. 3D), said drain terminal of the first passgate transistor being electrically connected to one of the first and second storage nodes (drain of pass transistor N4 connected to first storage node S2, FIG. 3D); and a read circuit including a word read line (read word line RWL, FIG. 3D), a first read transistor (transistor N7, FIG. 3D), and a second read transistor (transistor N5, FIG. 3D), said first and second read transistors including respective gate, source, and drain terminals (FIG. 3D), said gate terminal of the first read transistor being electrically connected to the first storage node (gate of transistor N7 connected to storage node S2, FIG. 3D); said gate terminal of the second read transistor being electrically connected to the word read line (gate of transistor N5 connected to read word line RWL, FIG. 3D), said drain terminal of the first read transistor electrically connected to the source terminal of the second read transistor (drain of transistor N7 is connected to source of transistor N5, FIG. 3D).
Chang does not disclose a first pair of p-channel transistors electrically connected in series between the first voltage rail and the second storage node, said first pair of p-channel transistors including respective gate terminals electrically connected to the first storage node, a first pair of n-channel transistors electrically connected in series between the second storage node and the second voltage rail, said first pair of n-channel transistors including respective gate terminals electrically connected to the first storage node.
Greene does disclose an SRAM Configuration Cell for Low-Power Field Programmable Gate Arrays (FIG. 3A) comprising: a first pair of p-channel transistors (e.g., 16a and 16b, FIG. 3A) electrically connected in series between the first voltage rail (voltage rail 20, FIG. 3A) and the second storage node (output node Y, FIG. 3A), said first pair of p-channel transistors including respective gate terminals electrically connected to the first storage node (gate terminals of 16a and 16b both connected to output node Y!, FIG. 3A); a first pair of n-channel transistors (e.g., 18 a and 18b, FIG. 3A) electrically connected in series between the second storage node (output node Y, FIG. 3A) and the second voltage rail (voltage rail 22, FIG. 3A), said first pair of n-channel transistors including respective gate terminals electrically connected to the first storage node (gate terminals of 18a and 18b both connected to output node Y!, FIG. 3A).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the inverters of Chang’s memory cell with the transistors in series configuration of Greene to allow the inverter to have the PMOS and NMOS transistors in series structure as the claimed invention.
Regarding claim 3: Chang discloses an improved static random access (SRAM) cell (30, FIG. 3D), comprising: a second passgate transistor (pass transistor N3, FIG. 3D) including a gate terminal electrically connected to the word write line (gate of pass transistor N3 connected to word write line WWL, FIG. 3D).
Chang does not disclose a second pair of p-channel transistors electrically connected in series between the first voltage rail and the first storage node, said second pair of p-channel transistors including respective gate terminals electrically connected to the second storage node, a second pair of n-channel transistors electrically connected in series between the first storage node and the second voltage rail, said second pair of n-channel transistors including respective gate terminals electrically connected to the second storage node.
Greene does disclose an SRAM Configuration Cell for Low-Power Field Programmable Gate Arrays (FIG. 3A) comprising: disclose a second pair of p-channel transistors (e.g., 26a and 26b, FIG. 3A) electrically connected in series between the first voltage rail (voltage rail 20, FIG. 3A) and the first storage node (output node Y!, FIG. 3A), said second pair of p-channel transistors including respective gate terminals electrically connected to the second storage node (gate terminals of 26a and 26b both connected to output node Y, FIG. 3A), a second pair of n-channel transistors (e.g., 28a and 28b, FIG. 3A) electrically connected in series between the first storage node (output node Y!, FIG. 3A) and the second voltage rail (voltage rail 22, FIG. 3A), said second pair of n-channel transistors including respective gate terminals electrically connected to the second storage node (gate terminals of 28a and 28b both connected to output node Y!, FIG. 3A).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the inverters of Chang’s memory cell with the transistors in series configuration of Greene to allow the inverter to have the PMOS and NMOS transistors in series structure as the claimed invention.
Regarding claim 4: Chang discloses an improved static random access (SRAM) cell (30, FIG. 3D), comprising: a third p-channel transistor (transistor P2, FIG. 3D) electrically connected between the first voltage rail (node shared by transistors P1 and P2, FIG. 3D) and the first storage node (storage node S2, FIG. 3D), said third p-channel transistor including a gate terminal electrically connected to the second storage node (gate of transistor P2 connected to storage node S1, FIG. 3D), a third n-channel transistor (transistor N2, FIG. 3D) electrically connected between the first storage node (storage node S2, FIG. 3D) and the second voltage rail (ground shared by transistors N1 and N2, FIG. 3D), said third n-channel transistor including a gate terminal electrically connected to the second storage node (gate of transistor N2 connected to storage node S1, FIG. 3D).
Regarding claim 6: Chang discloses an improved static random access (SRAM) cell (30, FIG. 3D), wherein said first and second read transistors are n-channel transistors (transistors N7 and N5 respectively, FIG. 3D), the source terminal of the first read transistor is electrically connected to ground (source of transistor N7 is connected to ground, FIG. 3D).
Regarding claim 9: Chang discloses an improved static random access (SRAM) cell (30, FIG. 3D), , comprising a second bit line (bit line BL, FIG. 3D), a second passgate transistor (pass transistor N3, FIG. 3D) including a gate terminal electrically connected to the word write line (gate of pass transistor N3 connected to write word like WWL, FIG. 3D), said second passgate transistor electrically connected between the second bit line and the second storage node (pass transistor N3 between bit line BL and storage node S1, FIG. 3D), wherein said drain terminal of the second read transistor is electrically connected to the second bit line (drain of pass transistor N3 connected to bit line BL, FIG. 3D).
Claim(s) 5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20070242513 A1) in view of Greene et al. (US 20190172522 A1), in further view of Sachdev et al. (US 20100110773 A1).
Regarding claim 5: Chang does not disclose a memory cell wherein said first and second read transistors are p-channel transistors, the source terminal of the first read transistor is electrically connected to a voltage rail.
Sachdev does disclose a static random access memory (SRAM) cell (FIG. 26), wherein said first and second read transistors are p-channel transistors (read assist circuit 2502 can comprise of two PMOS transistors P1READ and P2READ, par. 110), the source terminal of the first read transistor is electrically connected to a voltage rail (source of transistor P1READ is coupled to supply voltage VDD, par. 110).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read circuit transistors of Chang and Greene with the transistor configuration of Sachdev to allow the read circuit to have the claimed arrangement of PMOS and NMOS transistors for reading operation.
Regarding claim 7: Chang does not disclose a memory cell wherein said first read transistor is a p-channel transistor, said second read transistor is an n-channel transistor, the source terminal of the first read transistor is electrically connected to a voltage rail.
Sachdev does disclose a static random access memory (SRAM) cell (FIG. 26), wherein said first read transistor is a p-channel transistor (transistor PREAD, FIG. 26a), said second read transistor is an n-channel transistor (transistor N¬READ, FIG. 26a), the source terminal of the first read transistor is electrically connected to a voltage rail (source of transistor PREAD connected to power supply VDD, par. 103, FIG. 26a).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read circuit transistors of Chang and Greene with the transistor configuration of Sachdev to allow the read circuit to have the claimed arrangement of PMOS and NMOS transistors for reading operation.
Regarding claim 8: Chang does not disclose a memory cell wherein said first read transistor is an n-channel transistor, said second read transistor is a p-channel transistor, the source terminal of the first read transistor is electrically connected to ground.
Sachdev does disclose a static random access memory (SRAM) cell (FIG. 26), wherein said first read transistor is an n-channel transistor (transistor N¬READ, FIG. 26b), said second read transistor is a p-channel transistor (transistor PREAD, FIG. 26b), the source terminal of the first read transistor is electrically connected to ground (source of transistor NREAD connected to ground potential, par. 106, FIG. 26a).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the read circuit transistors of Chang and Greene with the transistor configuration of Sachdev to allow the read circuit to have the claimed arrangement of PMOS and NMOS transistors for reading operation.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20070242513 A1) in view of Greene et al. (US 20190172522 A1), in view of Takeyama et al (US 20070194833 A1).
Regarding claim 10: Chang discloses an improved static random access (SRAM) cell (30, FIG. 3D), comprising: a second bit line (bit line BL, FIG. 3D), a second passgate transistor (pass transistor N3, FIG. 3D) including a gate terminal electrically connected to the word write line (gate of pass transistor N3 connected to write word like WWL, FIG. 3D), said second passgate transistor electrically connected between the second bit line and the second storage node (pass transistor N3 between bit line BL and storage node S1, FIG. 3D).
Chang does not disclose a third bit line, wherein said drain terminal of the second read transistor is electrically connected to the third bit line.
Takeyama does disclose a memory cell structure of SRAM (FIG. 2), comprising: a third bit line (read data bit line RBL, FIG. 2), wherein said drain terminal of the second read transistor (read transfer gate RT1, FIG. 2) is electrically connected to the third bit line (drain of gate RT1 is connected to read bit line RB1, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SRAM structure of Chang and Greene with the configuration of Takeyama to allow the system to read the data of the memory cell to outside devices such as other memory devices.
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20070242513 A1) in view of Greene et al. (US 20190172522 A1), in view of Ramaraju (US 20120195111 A1).
Regarding claim 21: Chang does not disclose a memory cell being a twelve transistor (12T) memory cell.
Ramaraju does disclose an SRAM bitcell architecture with a 12T SRAM cell (FIG. 2 and 5).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cell of Chang and Greene with the configuration of Ramaraju to allow the system to have twelve transistors in its arrangement like the claimed invention.
Claim(s) 22 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20070242513 A1) in view of Greene et al. (US 20190172522 A1), in view of Moharir (US 9490008 B1).
Regarding claim 22: Chang does not disclose a memory cell being a nine transistor (9T) memory cell.
Moharir does disclose SRAM bitcells with 9T versions (FIG. 3 and 10).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cell of Chang and Greene with the configuration of Moharir to allow the system to have nine transistors in its arrangement as the claimed invention.
Allowable Subject Matter
The following is an examiner’s statement of reasons for allowance:
Claims include allowable subject matter since the prior art made of record and
considered pertinent to the applicants’ disclosure, taken individually or in combination,
does not teach or suggest the claimed limitations having: a source terminal of the first passgate transistor being electrically connected to the first bit line and a drain terminal of the second read transistor being electrically connected to the first bit line, wherein writing data to a first storage node through the first bit line and reading data from that first storage node to the same first bit line as in claim 11; a second voltage rail, a first storage node, a second storage node, a first pair of p-channel transistors electrically connected in series between the first voltage rail and the first storage node, a drain terminal of a first p-channel transistor of the first pair of p-channel transistors being electrically connected to a source terminal of a second p-channel transistor of the first pair of p-channel transistors to define the first intermediate node, a second pair of p-channel transistors electrically connected in series between the first voltage rail and the second storage node, a first pair of n-channel transistors electrically connected in series between the first storage node and the second voltage rail, a drain terminal of a first n-channel transistor of the first pair of n-channel transistors being electrically connected to a source terminal of a second n-channel transistor of the first pair of n-channel transistors to define the second intermediate node as in claim 19.
Any comments considered necessary by applicant must be submitted no later
than the payment of the issue fee and, to avoid processing delays, should preferably
accompany the issue fee. Such submissions should be clearly labeled “Comments on
Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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