DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/04/2024 and 05/02/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first mounting surface side (claims 6-10) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-10 are objected to because of the following informalities:
Claim 1: the limitation “the second substrate is provided with a second IC configured to process the baseband signal on a second mounting surface facing the metal housing” should read “the second substrate is provided with a second IC on a second mounting surface facing the metal housing, the second IC configured to process the baseband signal”.
Claim 1 (line 14): a colon should be inserted after “a metal housing includes”.
Claims 4-5 recite the limitation “the diameter of the tunnel portion”. This limitation does not have exact antecedent basis, and should read “the diameter of the cross section of the tunnel portion” for consistency with claim 3.
Appropriate correction is required.
Claims 2-3 and 6-10 are objected to due to their dependency.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “wherein the first substrate is provided with a first IC configured to process the first high frequency signal and be electrically connected to the feeding line on a first mounting surface facing the metal housing”. This limitation is ambiguous. It is not clear if the feeding line is provided on the first mounting surface which faces the metal housing (as shown in fig. 3), or if the first IC is provided on a first mounting surface facing the metal housing. Clarification is required.
For examination purposes, this limitation is interpreted as “wherein the first substrate is provided with a first IC on a first mounting surface facing the metal housing, the first IC configured to process the high-frequency signal and be electrically connected to the feeding line”.
Claims 6-10 all recite the limitation “wherein the first substrate includes a ground layer on a first mounting surface side with respect to the feeding line”. However, it is not clear what this limitation is intended to mean. For example, how is the first mounting surface side different to the first mounting surface (10a)? Fig. 4 shows the ground layer (150) formed on the first mounting surface (10a), whereas Fig. 3 shows the ground layer (130) formed “above” the feeding line (141) and away from the first mounting surface (10a), so the term “with respect to the feeding line” is also not clear. Clarification is required.
Claims 2-5 are rejected due to their dependency.
Allowable Subject Matter
Claims 1-10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: The pertinent prior art, as a whole, or in combination, cannot be reasonably construed as adequately teaching or suggesting the elements and features of the claimed invention(s) as arranged, disposed, or provided in the manner as claimed by the Applicant.
For example, regarding claim 1, IDS document Pagaila et al. (US 2015/115394; “Pagaila”) discloses (fig. 6 below & fig. 7a), as best understood, “An antenna module (¶¶39-40, “semiconductor die 102 may also contain integrated passive devices (IPD). The IPDs can be used as front-end wireless RF components, which can be positioned between the antenna and transceiver”) comprising:
a first substrate (interconnect structure 150) configured to handle a high-frequency signal in a millimeter wave band (¶58, “operating up to 100 GHz”, “quad-band for mobile phones or other GSM communications”);
a second substrate (interconnect structure 140 ) arranged to overlap a portion of the first substrate in plan view, and configured to be electrically connected to the first substrate at the overlapped portion (¶51, “The interconnect structure 140 is electrically connected to conductive pillars 126”) and handle a baseband signal having a frequency band lower than that of the high-frequency signal (¶51, “The interconnect structure 140 is electrically connected to the active and passive devices within semiconductor die 102 and 130 to form functional electrical circuits according to the electrical design and function of the semiconductor die.” ¶39, “Each semiconductor die 102 includes analog or digital circuits, the circuit may include one or more transistors, diodes, and other circuit elements to implement baseband analog circuits or digital circuits”);
wherein the first substrate (150) is provided with a first IC (semiconductor die 102) on a first mounting surface, the first IC configured to process the high-frequency signal and be electrically connected to the feeding line (¶¶39-40)
the second substrate (140) is provided with a second IC (semiconductor die 130) on a second mounting surface (lower surface of second substrate 140), the second IC configured to process the baseband signal (¶39 & ¶51),
a first accommodation space configured to accommodate the first IC (102),
a second accommodation space configured to accommodate the second IC (130), and
a shielding wall (110) provided between the first accommodation space and the second accommodation space (¶49, “Semiconductor die 102 and 130 may generate or be susceptible to undesired EMI, RFI, or other inter-device interference. Shielding layer 110 provides a cost effective and simple approach to reducing the EMI, RFI, or other interference between semiconductor die 102 and 130”)”.
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Pagalia teaches an antenna element (¶58, “The IPDs in semiconductor die 172 and 182 provide the electrical characteristics needed for high frequency applications”) and a feeding line to the antenna element (implicit, not shown).
However, Pagaila does not teach, or suggest, the first substrate includes an antenna element and a feeding line to the antenna element, and a metal housing to which the first substrate and the second substrate are attached,
the first IC is provided on a first mounting surface facing the metal housing,
the second IC is provided on a second mounting surface facing the metal housing, the first and second accommodation spaces included in the metal housing, the shielding wall is arranged to overlap the feeding line in plan view, and at least one of the shielding wall and the first substrate includes a non-interference portion configured to reduce interference between the shielding wall and the feeding line.
Kim et al. (US 2020/0259269; “Kim”) disclose (fig. 2F below) “An antenna module (title, chip antenna module 1) comprising:
a first substrate (substrate 10) that includes an antenna element (chip antenna 100) and a feeding line (wiring vias 1230a) to the antenna element (100) and configured to handle a high-frequency signal in a millimeter wave band (¶60, “The chip antenna module may operate in a radio-frequency (RF) range, for example, in a frequency band of 3 GHz or higher, or in a band of 20 GHz to 40 GHz”);
a second substrate (any of the layers below the IC 1300a) arranged to overlap a portion of the first substrate (10) in plan view,
wherein the first substrate (10) is provided with a first IC (1300a) configured to process the high-frequency signal (¶101, “the IC 1300a generates an RF signal in a mmWave band using the base band signal and the power”) and be electrically connected to the feeding line (wiring vias 1230a) on a first mounting surface (lower surface of first substrate 10),
a first accommodation space (¶97, “an IC 1300 a disposed in the accommodation hole of the support member 1355 a”) configured to accommodate the first IC (1300a),
a second accommodation space (accommodation space 1306a),
and a shielding wall (encapsulant 1305a) provided between the first accommodation space (accommodation hole of support member 1355a) and the second accommodation space (1306a), the shielding wall is arranged to overlap the feeding line in plan view”.
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Kim does not teach, or suggest, a second substrate configured to be electrically connected to the first substrate at the overlapped portion and handle a baseband signal having a frequency band lower than the frequency of the high frequency signal; and a metal housing to which the first substrate and the second substrate are attached, a first mounting surface facing the metal housing, the second substrate is provided with a second IC on a second mounting surface facing the metal housing, the second IC configured to process the baseband signal, the metal housing includes the first accommodation space and the second accommodation space configured to accommodate the second IC, and at least one of the shielding wall and the first substrate includes a non-interference portion configured to reduce interference between the shielding wall and the feeding line.
Matthews et al. (US 6,686,649; “Matthews”) disclose (fig. 1 & fig. 6 below) “An antenna module (abstract, transceiver package with antenna section) comprising:
a first substrate (dielectric cap 154A) that includes an antenna element (antenna 156) and a feeding line to the antenna element (antenna trace 136, and antenna strap 158);
a second substrate (multi-chip substrate 102A) arranged to overlap a portion of the first substrate (154A) in plan view, and configured to be electrically connected to the first substrate at the overlapped portion (by ground vias 126, upper ground trace 122, conductive adhesive 181A, and sidewall 162);
and a metal housing (shield 152B) to which the first substrate (154A) and the second substrate (102A) are attached,
a first IC (col. 3, line 39, “an electronic component 104 such as an integrated circuit”), the first IC configured to process the high-frequency signal and be electrically connected to the feeding line (col. 9, lines 21-; “During use, electronic component 104 generates an em signal on bond pad 108B, an RF signal, e.g., a 2.5 GHz signal although other frequency signals can be used”),
the second substrate (102A) is provided with a second IC (104A, IC) on a second mounting surface facing the metal housing (152B),
the metal housing (152B) includes:
a first accommodation space configured to accommodate the first IC (104),
a second accommodation space configured to accommodate the second IC (104A), and
a shielding wall (col. 12, lines 21-; “shields 152A, 152B are electrically connected directly to one another by an electrically conductive bridge portion 620, which extends across boundary 504”) provided between the first accommodation space and the second accommodation space”.
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Matthews does not teach, or suggest, the first substrate is configured to handle a high-frequency signal in a millimeter wave band, a second substrate configured to handle a baseband signal having a frequency band lower than that of the high signal; wherein the first substrate is provided with the first IC on a mounting surface facing the metal housing, the second IC is configured to process the baseband signal, the shielding wall is arranged to overlap the feeding line in plan view, and at least one of the shielding wall and the first substrate includes a non-interference portion configured to reduce interference between the shielding wall and the feeding line.
Claims 2-10 are allowable due to their dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANNA N HAMADYK whose telephone number is (703)756-1672. The examiner can normally be reached 7:30 am - 5:00 pm.
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/ANNA N HAMADYK/Examiner, Art Unit 2845
/DIMARY S LOPEZ CRUZ/Supervisory Patent Examiner, Art Unit 2845