Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Examiner’s Remark
At the time of writing of the instant action, the Examiner is aware of potential avenues for advancing prosecution and encourages Applicant to contact the Examiner to advance prosecution.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Khatri et al (U.S. Pat App Pub 2023/0010345 A1), hereinafter referred to as Khatri, in view of Girkar et al (U.S. Pat App Pub 2020/0007332 A1), hereinafter referred to as Girkar, and in further view of Driscoll (U.S. Pat App Pub 2023/0244821 A1), hereinafter referred to as Driscoll.
Re claim 1: Khatri teaches a memory device comprising: a one-time programmable (OTP) memory comprising a plurality of regions; a memory controller comprising more than one core, each of the more than one core associated with a respective OTP access key; and an OTP access controller (¶29; ¶36; Fig 6; ¶45; ¶65; ¶69; ¶74; ¶81; ¶94).
Girkar teaches an OTP access controller: assign a first access authority to a first core from the more than one core to access a first subset of regions from the plurality of regions based on a first OTP access key; and assign a second access authority to a second core from the more than one core to access a second subset of regions from the plurality of regions based on a second OTP access key (Fig 3; ¶56-¶64; Fig 5; ¶71-¶73).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Khatri with the teachings of Girkar, for the purpose of providing predictable variations in the art of multi-core processing environments via efficient enforcement of compartmentalization of sensitive/protected data.
Driscoll teaches an OTP access controller, assign a first access authority to a first core from the more than one core to access a first subset of regions from the plurality of regions based on a first OTP access key; and assign a second access authority to a second core from the more than one core to access a second subset of regions from the plurality of regions based on a second OTP access key (Fig 2; ¶28-¶32), wherein the first subset of regions and the second subset of regions comprise a common region that can be accessed based on the first access authority and the second access authority (Fig 1; ¶13-¶15; ¶21-¶22; ¶25-¶26; ¶29-¶31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Khatri and Girkar with the teachings of Driscoll, for the purpose of providing predictable variations in the art of multi-core processing environments where Driscoll includes a shared memory accessible to a plurality of cores and each core has memory exclusively accessible to an associated core in a plurality of cores. Doing so has the known benefit of securely sharing crypto-states amongst a plurality of cores in a multi-core system.
Re claim 2: The combination of Khatri, Girkar and Driscoll teaches the common region is a region in which sharing data shared by the first core and the second core are stored (Driscoll: Fig 1; ¶13-¶15; ¶21-¶22; ¶25-¶26; ¶29-¶31).
Re claim 18: Khatri teaches a memory device comprising: a memory controller comprising a plurality of cores, each of the plurality of cores associated with a respective OTP access key; and a one-time programmable (OTP) memory comprising a plurality of regions (¶29; ¶36; Fig 6; ¶45; ¶65; ¶69; ¶74; ¶81; ¶94).
Girkar teaches assign a first access authority to access the first subset of regions and the second subset of regions to the first core based on a first OTP access key corresponding to the first core; and assign a second access authority to access the second subset of regions and the third subset of regions to the second core based on a second OTP access key corresponding to the second core (Fig 3; ¶56-¶64; Fig 5; ¶71-¶73).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Khatri with the teachings of Girkar, for the purpose of providing predictable variations in the art of multi-core processing environments via efficient enforcement of compartmentalization of sensitive/protected data.
Driscoll teaches the memory controller is configured to: assign a first access authority to access the first subset of regions and the second subset of regions to the first core based on a first OTP access key corresponding to the first core; and assign a second access authority to access the second subset of regions and the third subset of regions to the second core based on a second OTP access key corresponding to the second core (Fig 2; ¶28-¶32), a first subset of regions that stores data only a first core uses, a second subset of regions that stores data which the first core and a second core use, and a third subset of regions that stores data which only the second core uses (Fig 1; ¶13-¶15; ¶21-¶22; ¶25-¶26; ¶29-¶31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Khatri and Girkar with the teachings of Driscoll, for the purpose of providing predictable variations in the art of multi-core processing environments where Driscoll includes a shared memory accessible to a plurality of cores and each core has memory exclusively accessible to an associated core in a plurality of cores. Doing so has the known benefit of securely sharing crypto-states amongst a plurality of cores in a multi-core system.
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Khatri et al (U.S. Pat App Pub 2023/0010345 A1), hereinafter referred to as Khatri, in view of Fernández Gutiérrez (U.S. Pat App Pub 2012/0331307 A1), hereinafter referred to as Fernández, in further view of Driscoll (U.S. Pat App Pub 2023/0244821 A1), hereinafter referred to as Driscoll.
Re claim 13: Khatri teaches an operating method of a memory device, the memory device comprising a memory controller, one-time programmable (OTP) memory and first subset of regions of the “OTP memory” (¶29; ¶36; Fig 6; ¶45; ¶65; ¶69; ¶74; ¶81; ¶94).
Fernández teaches generating a first authentication code associated with access authentication for authenticating an access of a first core of the memory controller to the OTP “memory”, based on a first OTP access key corresponding to the first core; generating a second authentication code associated with the access authentication, based on a first authentication key stored in key region of the memory controller, the first authentication key corresponding to the first OTP access key; comparing the first authentication code and the second authentication code (Fig 5; ¶95-¶112; ¶281-¶291; Fig 19; ¶396-¶406).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Khatri with the teachings of Fernández, for the purpose of providing the known benefit of preventing Instruction Cache Attacks as taught by Fernández, ¶492.
Driscoll teaches assigning an access authority to the first core to access a first subset of regions of the OTP memory, based on that the first authentication code and the second authentication code being equal, wherein the first subset of regions comprises a region storing sharing data that is shared by the first core and a second core of the memory controller (Fig 1; ¶13-¶15; ¶21-¶22; ¶25-¶26; ¶29-¶31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Khatri and Fernández with the teachings of Driscoll, for the purpose of providing predictable variations in the art of multi-core processing environments where Driscoll includes a shared memory accessible to a plurality of cores and each core has memory exclusively accessible to an associated core in a plurality of cores. Doing so has the known benefit of securely sharing crypto-states amongst a plurality of cores in a multi-core system.
Allowable Subject Matter
Claims 3-12, 14-17, 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Examiner's Note:
The Examiner identified and designated “the particular part[s] [of the references] relied on” as provided in 37 C.F.R § 1.104(c)(2).
A reference is not limited to the disclosure of specific working examples. In re Mills, 470 F.2d 649, 651 (CCPA 1972); In re Fracalossi, 681 F.2d 792, 794 n.1 (CCPA 1982) (A prior art reference’s disclosure is not limited to its examples.). Nor do disclosed examples teach away from a reference’s broader disclosure. In re Susi, 440 F.2d 442, 446 n.3 (CCPA 1971); In re Boe, 355 F.2d 961, 965 (CCPA 1966) (All of the disclosures in a prior art reference “must be evaluated for what they fairly teach one of ordinary skill in the art.”).
“The prima facie case is merely a procedural device that enables an appropriate shift of the burden of production.” Hyatt v. Dudas, 492 F.3d. 1365, 1369 (Fed. Cir. 2007) (citing In re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992)). The court has, thus, held that the USPTO carries its procedural burden of establishing a prima facie case when its rejection satisfies the requirements of 35 U.S.C. § 132 by notifying the applicant of the reasons for rejection, “together with such information and references as may be useful in judging of the propriety of continuing the prosecution of [the] application.” See In re Jung, 637 F.3d 1356, 1362 (Fed. Cir. 2011).
MPEP 2123 [R – 08.2012] states: "The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain." In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)).
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A reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill the art, including nonpreferred embodiments. Merck & Co. v. Biocraft Laboratories, 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989). See also Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005) (reference disclosing optional inclusion of a particular component teaches compositions that both do and do not contain that component); Celeritas Technologies Ltd. v. Rockwell International Corp., 150 F.3d 1354, 1361, 47 USPQ2d 1516, 1522-23 (Fed. Cir. 1998) (The court held that the prior art anticipated the claims even though it taught away from the claimed invention. "The fact that a modem with a single carrier data signal is shown to be less than optimal does not vitiate the fact that it is disclosed.").
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. See: Ralston Purina Co. v. FarMar-Co, Inc., 772 F.2d 1570, 1575 (Fed. Cir. 1985), In re Kaslow, 707 F.2d 1366, 1375 (Fed. Cir. 1983), Ariad Pharmaceuticals, Inc. v. Eli Lilly and Co., 598 F.3d 1336, 1352 (Fed. Cir. 2010), Purdue Pharma L.P. v. Faulding, Inc., 230 F.3d 1320, 1323 (Fed. Cir. 2000), Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1560 (Fed. Cir. 1991) and TurboCare Div. of Demag Delavel Turbomachinery Corp. v. Gen. Elec. Co., 264 F.3d 1111, 1118 (Fed. Cir. 2001)
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTOL-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DARREN B SCHWARTZ whose telephone number is (571)270-3850. The examiner can normally be reached 9am-7pm EST, Monday-Thursday, 9am-5pm EST, Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph P Hirl can be reached at (571)272-3685. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DARREN B SCHWARTZ/Primary Examiner, Art Unit 2435