DETAILED ACTION
This office action is in response to the application filed on 11/04/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/04/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kumar US 2021/0313876 .
Regarding Claim 1, Kumar teaches (Figures 1-7) A circuit (Fig. 1) comprising: a first switching leg (q3-q4) coupled between a first direct current (DC) terminal and a second DC terminal (210-212); a second switching leg (q1-q2) coupled between the first DC terminal and the second DC terminal (210-212); a first switch and a second switch, arranged in the first switching leg (q3-q4), wherein the first switch and the second switch are coupled to a first alternating current (AC) line (at 204); a third switch and a fourth switch (q1-q2), arranged in the second switching leg, wherein the third switch and the fourth switch are coupled to a second AC line (202) at a first node (sw) of the second switching leg, further wherein the fourth switch is coupled to a ground (gnd); and a voltage source (134, 114, 330, 126 and 332), arranged between the ground (gnd) and the first node of the second switching leg (sw), wherein an output of the voltage source is coupled to a first capacitor (C2). (For example: Par. 39-53)
Regarding Claim 2, Kumar teaches (Figures 1-7) wherein the voltage source (134, 114, 330, 126 and 332) is configured to produce a first voltage that is proportional and opposite in polarity to a second voltage across the fourth transistor (Q2, see par. 53). (For example: Par. 39-53)
Regarding Claim 10, Kumar teaches (Figures 1-7) a system (Fig. 1.) comprising: an alternating current input (with 202 and 204) having a first AC terminal and a second AC terminal (206); a first switching leg (q3-q4) and a second switching leg (q1-q2) coupled between a first direct current (DC) terminal and a second DC terminal (210-212), wherein the first switching leg is coupled to the first AC terminal (204), and wherein the second switching leg is coupled to the second AC terminal (202); a filter (208) disposed between the AC input and the first and second switching legs; a first transistor (q1) disposed in the second switching leg between the first DC terminal and a first node (210 and sw); a second transistor (q2) disposed in the second switching leg between the first node and the second DC terminal (sw and 212); and a voltage source (134, 114, 330, 126 and 332) coupled to the first node (sw) and coupled to a ground (gnd) and having an output coupled to a capacitor (c2). (For example: Par. 39-53)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-5 and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Sakai US 2013/0147419. (Examiner’s Note: Couple can de direct or indirect coupling including magnetically coupled)
Regarding Claims 3 and 11, Kumar teaches (Figures 1-7) wherein the voltage source (134, 114, 330, 126 and 332) comprises: an operational amplifier (134) having an output of the amplifier is coupled to the ground via the first capacitor (c2, see fig. 3). (For example: Par. 39-53)
Kumar does not teach an operational amplifier having an inverting input and a non-inverting input, wherein the non-inverting input is coupled to the first node of the second switching leg, and wherein the inverting input is coupled to the second DC terminal.
Sakai teaches (Figures 1-3) an operational amplifier (3) having an inverting input and a non-inverting input (inputs to 3), wherein the non-inverting input is coupled to the first node of the second switching leg (at 41 with 1-22), and wherein the inverting input is coupled to the second DC terminal (at 41 with 1-2). (For example: Par. 21-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include an operational amplifier having an inverting input and a non-inverting input, wherein the non-inverting input is coupled to the first node of the second switching leg, and wherein the inverting input is coupled to the second DC terminal, as taught by Sakai to provide common mode voltage cancellation.
Regarding Claims 4 and 12, Kumar teaches (Figures 1-7) wherein the voltage source (134, 114, 330, 126 and 332) comprises: an operational amplifier (134) having an output of the amplifier is coupled to the ground via the first capacitor (c2, see fig. 3). (For example: Par. 39-53)
Kumar does not teach an operational amplifier having an inverting input and a non-inverting input, wherein the non-inverting input is coupled to the first node of the second switching leg, and wherein the inverting input is coupled to the first DC terminal.
Sakai teaches (Figures 1-3) an operational amplifier (3) having an inverting input and a non-inverting input (inputs), wherein the non-inverting input is coupled to the first node of the second switching leg (at 41 with 1-2), and wherein the inverting input is coupled to the first DC terminal(at 41 with 1-2). (For example: Par. 21-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include an operational amplifier having an inverting input and a non-inverting input, wherein the non-inverting input is coupled to the first node of the second switching leg, and wherein the inverting input is coupled to the first DC terminal, as taught by Sakai to provide common mode voltage cancellation.
Regarding Claims 5 and 13, Kumar teaches (Figures 1-7) wherein the voltage source (134, 114, 330, 126 and 332) comprises: an operational amplifier (134) having an output of the amplifier is coupled to the ground via the first capacitor (c2, see fig. 3). (For example: Par. 39-53)
Kumar does not teach an operational amplifier having an inverting input and a non-inverting input, wherein the inverting input is coupled to the first node of the second switching leg, and wherein the non-inverting input is coupled to the second DC terminal.
Sakai teaches (Figures 1-3) an operational amplifier () having an inverting input and a non-inverting input (input of 3), wherein the inverting input is coupled to the first node of the second switching leg (at 41 with 1-2), and wherein the non-inverting input is coupled to the second DC terminal (at 41 with 1-2). (For example: Par. 21-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include an operational amplifier having an inverting input and a non-inverting input, wherein the inverting input is coupled to the first node of the second switching leg, and wherein the non-inverting input is coupled to the second DC terminal, as taught by Sakai to provide common mode voltage cancellation.
Claim(s) 6-7, 14-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Gonthier US 2020/0381992. (Examiner’s Note: Couple can de direct or indirect coupling including magnetically coupled)
Regarding Claim 6, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the voltage source comprises: a transformer having a first winding and a second winding, wherein the first winding is coupled to the second AC line and coupled to the ground via the first capacitor.
Gonthier teaches (Figure 6) wherein the voltage source (bottom converter) comprises: a transformer (6) having a first winding (61) and a second winding (67), wherein the first winding is coupled to the second AC line (see fig. 6, with D6) and coupled to the ground via the first capacitor (with c62). (For example: Par. 86-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include wherein the voltage source comprises: a transformer having a first winding and a second winding, wherein the first winding is coupled to the second AC line and coupled to the ground via the first capacitor, as taught by Gonthier to protect the system by discharging the charge of the system capacitor.
Regarding Claims 7 and 15, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the second winding is coupled to the first node of the second leg and to the second DC terminal.
Gonthier teaches (Figure 6) wherein the second winding (67) is coupled to the first node of the second leg (at 25) and to the second DC terminal (with the connection at 25 and Vdd1). (For example: Par. 86-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include wherein the second winding is coupled to the first node of the second leg and to the second DC terminal, as taught by Gonthier to protect the system by discharging the charge of the system capacitor.
Regarding Claim 14, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the voltage source comprises a transformer having a first winding coupled to the first node and to the ground via the capacitor.
Gonthier teaches (Figure 6) wherein the voltage source (bottom converter) comprises a transformer (6) having a first winding (61) coupled to the first node (with d5 or d6) and to the ground via the capacitor (c62). (For example: Par. 86-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include wherein the voltage source comprises a transformer having a first winding coupled to the first node and to the ground via the capacitor, as taught by Gonthier to protect the system by discharging the charge of the system capacitor.
Regarding Claim 16, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the voltage source comprises a second winding coupled to the first DC terminal and the first node
Gonthier teaches (Figure 6) wherein the voltage source comprises a second winding (67) coupled to the first DC terminal and the first node (with the connection at 25 and Vdd1). (For example: Par. 86-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include wherein the voltage source comprises a second winding coupled to the first DC terminal and the first node, as taught by Gonthier to protect the system by discharging the charge of the system capacitor.
Regarding Claim 18, Kumar teaches (Figures 1-7) comprising a totem pole bridgeless power factor correction rectifier that includes the first switching leg and the second switching leg (see fig. 3a). (For example: Par. 39-53)
Claim(s) 8-9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Gonthier US 2020/0381992 and further in view of Tsuruya US 2005/0083132. (Examiner’s Note: Couple can de direct or indirect coupling including magnetically coupled)
Regarding Claim 8, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the first winding and the second winding have different polarities.
Tsuruya teaches (Figures 10-11 and 14) wherein the first winding and the second winding have different polarities (N11 and n21). (For example: Par. 21-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include and wherein the first winding and the second winding have different polarities, as taught by Tsuruya to reduce unwanted noises caused by leakage currents in the system.
Regarding Claim 9, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the second winding is coupled to the first DC terminal and the first node of the second leg, and wherein the first winding and the second winding have a same polarity.
Gonthier teaches (Figure 6) wherein the second winding (67) is coupled to the first DC terminal and the first node of the second leg (at 25 with Vdd1). (For example: Par. 86-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include wherein the second winding is coupled to the first DC terminal and the first node of the second leg, as taught by Gonthier to protect the system by discharging the charge of the system capacitor.
Kumar as modified does not teach wherein the first winding and the second winding have a same polarity.
Tsuruya teaches (Figures 10-11 and 14) wherein the first winding and the second winding have a same polarity (N11 and N22). (For example: Par. 21-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include and wherein the first winding and the second winding have a same polarity, as taught by Tsuruya to reduce unwanted noises caused by leakage currents in the system.
Regarding Claim 17, Kumar teaches (Figures 1-7) the circuit.
Kumar does not teach wherein the voltage source comprises a second winding coupled to the first node and to the second DC terminal, and wherein the first winding has an opposite polarity relative to the second winding.
Gonthier teaches (Figure 6) wherein the voltage source (bottom converter) comprises a second winding (67) coupled to the first node and to the second DC terminal (with the connection at 25 and Vdd1). (For example: Par. 86-93)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include wherein the voltage source comprises a second winding coupled to the first node and to the second DC terminal, as taught by Gonthier to protect the system by discharging the charge of the system capacitor.
Kumar as modified does not teach wherein the first winding and the second winding have different polarities.
Tsuruya teaches (Figures 10-11 and 14) wherein the first winding and the second winding have different polarities (N11 and n21). (For example: Par. 21-31)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include and wherein the first winding and the second winding have different polarities, as taught by Tsuruya to reduce unwanted noises caused by leakage currents in the system.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Pervaiz US 11575314.
Regarding Claim 19, Kumar teaches (Figures 1-7) a method comprising: controlling a voltage converter (at fig. 1), sensing a first voltage at a first node of the second switching leg (with 114, Vsense); and applying a second voltage to a first capacitor (C2), wherein a value of the second voltage is proportional to a value of the first voltage (par. 53), thereby injecting a first current to ground via the first capacitor (C2 see fig. 3-5), wherein the first current compensates a second current between the first node and ground (compensation current determined by 134 and noise current). (For example: Par. 39-53)
Kumar does not teach including transmitting first control signals to switch a first switching leg at a first frequency and transmitting second control signals to switch a second switching leg at a second frequency that is lower than the first frequency.
Pervaiz teaches (Figures 3) including transmitting first control signals (sent to s1-s2) to switch a first switching leg at a first frequency (at s1-s2) and transmitting second control signals (sent to s3-s4) to switch a second switching leg (s3-s4) at a second frequency that is lower than the first frequency (Fig. 3b). (For example: Col. 11 lines 45-67 and Col. 12 lines 1-50)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Kumar to include including transmitting first control signals to switch a first switching leg at a first frequency and transmitting second control signals to switch a second switching leg at a second frequency that is lower than the first frequency; as taught by Pervaiz to reduce conduction and switching losses in the system.
Regarding Claim 20, Kumar teaches (Figures 1-7) the circuit. wherein the first voltage (voltage at sw) comprises a voltage between the first node and a positive direct current (DC) terminal of the voltage converter or a voltage between the first node and a negative DC terminal of the voltage converter (se fig. 3a), and wherein the ground (gnd) is an earth ground or a chassis ground (e.g. 110). (For example: Par. 39-53)
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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