Prosecution Insights
Last updated: August 16, 2026
Application No. 18/936,405

WIRING STRUCTURE AND AMPLIFIER

Non-Final OA §102§103
Filed
Nov 04, 2024
Priority
Nov 06, 2023 — JP 2023-189222
Examiner
OUTTEN, SAMUEL S
Art Unit
Tech Center
Assignee
Sumitomo Electric Industries Ltd.
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
520 granted / 658 resolved
+19.0% vs TC avg
Strong +20% interview lift
Without
With
+20.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
35 currently pending
Career history
683
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
52.5%
+12.5% vs TC avg
§102
21.2%
-18.8% vs TC avg
§112
19.9%
-20.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 658 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitahara (US Patent 5977845). As per claim 1: Kitahara discloses in Figs. 1-14: A wiring structure comprising a MIM capacitor and a helical wiring (conductive films 1a, 2a, 3a, 4a), comprising: a substrate (100) having a main surface and a back surface; and a plurality of wiring layers (layers A-D) sequentially stacked on or above the main surface, wherein the plurality of wiring layers include a first wiring layer being a wiring layer closest to the substrate, a second wiring layer provided on or above the first wiring layer, and a third wiring layer provided on or above the second wiring layer, wherein the MIM capacitor includes a first electrode (conductive film 2b) included in the second wiring layer, a second electrode (conductive film 3b) included in the third wiring layer, and a first electrically insulating layer (layer 102, col. 4 lines 45-57) provided between the first electrode and the second electrode, and wherein the helical wiring includes a first wiring (1a) included in the first wiring layer, a second wiring (2a) included in the second wiring layer, and a third wiring (3a) included in the third wiring layer. As per claim 2: Kitahara discloses in Figs. 1-14: a fourth wiring (1c) provided between the MIM capacitor and the substrate and included in the first wiring layer; and one or more first vias (through hole 12b) connecting the first electrode to the fourth wiring (as seen in Fig. 1). As per claim 11: Kitahara discloses in Figs. 1-14: the plurality of wiring layers further include a fourth wiring layer (layer D) stacked on or above the third wiring layer, and wherein the fourth wiring layer includes a sixth wiring (conductive film 4) provided above the MIM capacitor. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kitahara (US Patent 5977845) in view of Sankman et al. (US PGPub 20160088736). As per claim 12: Kitahara discloses in Figs. 1-14: a second electrically insulating layer (layer 101) interposed between the first wiring layer and the second wiring layer; and a third electrically insulating layer (102) interposed between the second wiring layer and the third wiring layer, Kitihara does not disclose: wherein a thickness of the first electrically insulating layer is smaller than each of thicknesses of the second electrically insulating layer and the third electrically insulating layer, and wherein a dielectric constant of the first electrically insulating layer is larger than each of dielectric constants of the second electrically insulating layer and the third electrically insulating layer. Sankman et al. discloses in Figs. 1A-C: Multi-layer circuits comprising inductors ([0016]) and a capacitor (electrodes 105 & 104 with dielectric adhesion layer 106), wherein an insulating layer (adhesion layer 106) between an MIM capacitor (electrodes 105 & 104 with dielectric adhesion layer 106) is thinner (as seen in Figs. 1A & 1C) with a higher dielectric constant ([0013,0017], wherein silicon nitride has a higher dielectric constant than silica) than insulating layers between other conductors in the circuit. At the time of filing, it would have been obvious to one of ordinary skill in the art to form the circuit of Kitahara such that a thickness of the first electrically insulating layer is smaller than each of thicknesses of the second electrically insulating layer and the third electrically insulating layer, and wherein a dielectric constant of the first electrically insulating layer is larger than each of dielectric constants of the second electrically insulating layer and the third electrically insulating layer, to provide the benefit of controlling the capacitance of the capacitor through the design parameters of dielectric constant and dielectric thickness, which are well-known in the art to determine the capacitance of a capacitor, and as illustrated by Sankman et al. (Figure 1, [0014]). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kitahara (US Patent 5977845) in view of Hikioka et al. (US PGPub 20090315662). As per claim 13: Kitahara does not disclose: a transistor provided on or above the substrate shared with the wiring structure. Hikioka et al. discloses in Fig. 17A-B: A multilayer LC circuit (inductor 34, capacitor 35) incorporated on the same common substrate (30) as a transistor (36). At the time of filing, it would have been obvious to one of ordinary skill in the art to incorporate the wiring structure of Kitahara with a transistor on the substrate to provide the benefit of consolidating multiple parts of a circuit in a single package as shown by Hikioka et al. to provide the benefit of miniaturization and simplicity, as shown in Figs 17A-B of Hikioka et al. Allowable Subject Matter Claims 3-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the limitations of claims 3 & 4 in combination with the limitations of the claims upon which they depend were not disclosed or rendered obvious over the prior art of record, which is the closest relevant prior art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL S OUTTEN whose telephone number is (571)270-7123. The examiner can normally be reached M-F: 9:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at (571) 272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Samuel S Outten/Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Nov 04, 2024
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+20.2%)
2y 6m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 658 resolved cases by this examiner. Grant probability derived from career allowance rate.

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