The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1, 4-8, 11-12, 14, 17-26 are presented for examination
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
Claim 1, 4-8, 11-12, 14, 17-26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 3-20 of patent number 12147542. The table listed below shows the similarity between the two and highlight the differences.
Instant Application 18936509
Patent 12147542
(Currently Amended) A field-deployable hardware apparatus comprising:
a stackable housing comprising one or more attachment features configured to secure the stackable housing to an adjacent housing of an adjacent hardware apparatus;
a graphical processing unit disposed within the stackable housing, the graphical
processing unit comprising a first plurality of processor cores;
a general-purpose processor disposed within the stackable housing, the general-purpose processor comprising a second plurality of processor cores;
at least a binary unit system disposed within the stackable housing and connecting the graphical processing unit to the general-purpose processor; and
a memory communicatively connected to at least a core of the first plurality of cores and
the second plurality of cores, the memory containing instructions configuring the
at least a core to execute a hypervisor, wherein the hypervisor generates a virtual
environment on the at least a core.
(Currently Amended) A field-deployable hardware apparatus comprising:
a stackable housing comprising one or more attachment features configured to secure the stackable housing to, and above or below, an adjacent housing of an adjacent field-deployable hardware apparatus, wherein the stackable housing comprises a waterproof construction including one or more sealable openings;
a graphical processing unit disposed within the stackable housing, the graphical processing unit comprising a first plurality of processor cores;
a general-purpose processor disposed within the stackable housing, the general-purpose processor comprising a second plurality of processor cores;
at least a binary unit system disposed within the stackable housing and connecting the graphical processing unit to the general-purpose processor; and
a memory communicatively connected to at least a core of the first plurality of cores and the second plurality of cores, the memory containing instructions configuring the at least a core to execute a hypervisor, wherein the hypervisor generates a virtual environment on the at least a core.
4. (Original) The apparatus of claim 1, wherein the general-purpose processor further comprises a reduced instruction set computer.
5. (Original) The apparatus of claim 1, wherein the memory further comprises a per- processor memory.
6. (Original) The apparatus of claim 1, wherein the memory comprises a boot partition.
7. (Original) The apparatus of claim 6, wherein the boot partition comprises a trusted boot module.
8. (Original) The apparatus of claim 7, wherein the trusted boot module is configured to perform a secure proof protocol.
4. (Original) The apparatus of claim 1, wherein the general-purpose processor further comprises a reduced instruction set computer.
5. (Original) The apparatus of claim 1, wherein the memory further comprises a per- processor memory.
6. (Original) The apparatus of claim 1, wherein the memory comprises a boot partition.
7. (Original) The apparatus of claim 6, wherein the boot partition comprises a trusted boot module.
8. (Original) The apparatus of claim 7, wherein the trusted boot module is configured to perform a secure proof protocol.
11. (Original) The apparatus of claim 1, wherein the hypervisor includes a bare metal hypervisor.
12. (Original) The apparatus of claim 1, wherein the hypervisor includes a Type 2 hypervisor.
14. (Original) The apparatus of claim 1, wherein the hypervisor is configured to execute at least an operating system.
19. (Currently Amended) The apparatus of claim 1, wherein the memory contains instructions configuring the at least a core to verify a compliance of the hardware apparatus with at least a pre-determined safety standard from a trusted repository by monitoring an adherence of the hardware apparatus to a pre-defined operational rule.
20. (Original) The apparatus of claim 1 further comprising at least a high-density input and output port communicatively connected to the graphical processing unit and the general- purpose processor.
11. (Original) The apparatus of claim 1, wherein the hypervisor includes a bare metal hypervisor.
12. (Original) The apparatus of claim 1, wherein the hypervisor includes a Type 2 hypervisor.
14. (Original) The apparatus of claim 1, wherein the hypervisor is configured to execute at least an operating system.
19. (Original) The apparatus of claim 1, wherein the memory contains instructions configuring the at least a core to verify a compliance of the hardware apparatus with at least a pre-determined safety standard from a trusted repository by monitoring an adherence of the hardware apparatus to the pre-defined operational rule.
20. (Original) The apparatus of claim 1 further comprising at least a high-density input and output port communicatively connected to the graphical processing unit and the general- purpose processor.
As shown from the table above, claims 1, 4-8, 11-12, 14, and 19-20 of patent 12147542 teaches the same concept of the instant application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-, 11-12, 14, 18, and 20-26 5 are rejected under 35 U.S.C. 103 as being unpatentable over Sharfi (US Patent Application 20230097002) in the view of Pappu (US Patent Application 20230109990).
As per claim 1, Sharfi teaches a field-deployable hardware [100, fig. 1] apparatus comprising:
a stackable housing [stackable boxes shown in figures 1 and 3] comprising one or more attachment features [stackable slider, fig1 and 3] configured to secure the stackable housing to an adjacent housing of an adjacent hardware apparatus [0040, fig. 3, as pointed out, the housing is made of multiple bricks that can be sliding and stackable together. For example, the top and bottom enclosures are slidable for ease of operation during stacking and unstacking of the modules].
a graphical processing unit [GPGPU, fig. 7] disposed within the stackable housing, the graphical processing unit comprising a first plurality of processor cores [0059, 0090, 0096, as the video processing unit is stackable contains FPGA].
a general-purpose processor [intel atom processor, fig. 18] disposed within the stackable housing, the general-purpose processor comprising a second plurality of processor cores [0088, 0083, 0088, intel atom processor in the housing which is a multicore processor].
at least a binary unit [switch module, fig. 18] system disposed within the stackable housing and connecting the graphical processing unit to the general-purpose processor [0011, 0088, as shown in figures 6, 8-9 multiple modules are connected together such as processor and GPU to form the apparatus].
Sharfi does not teach a memory communicatively connected to at least a core of the first plurality of cores and the second plurality of cores, the memory containing instructions configuring the at least a core to execute a hypervisor, wherein the hypervisor generates a virtual environment on the at least a core.
However, Pappu teaches a memory [441, fig. 4B] communicatively connected to at least a core [4460, fig. 4B] of the first plurality of cores and the second plurality of cores, the memory containing instructions configuring the at least a core to execute a hypervisor, wherein the hypervisor generates a virtual environment on the at least a core [0130, 0139, as pointed out the memory store code that run by the processor with a hypervisor program that can create virtual machine. For example, in the dedicated-process programming models, the graphics processing engines 431,432, N, may be shared by multiple VM/application partitions. The shared models require a system hypervisor to virtualize the graphics processing engines 431-432, N to allow access by each operating system. For single-partition systems without a hypervisor, the graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432, N to provide access to each process or application].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method of Pappu to provide a virtual machine environment where the system can be configured to emulate other system with different operating systems.
As per claim 4, Sharfi teaches the general-purpose processor further comprises a reduced instruction set computer [0083, 0088, processor module with any architecture can be used].
As per claim 5, Sharfi does not teach the memory further comprises a per-processor memory.
However, Pappu teaches the memory further comprises a per-processor memory [0084, 0120 core programmable with data in shared memory and memory couple to specific core of the processor].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method of Pappu to use specific memory for specific core of the processor.
As per claim 11, Sharfi does not teach the hypervisor includes a bare metal hypervisor.
However, Pappu teaches the hypervisor includes a bare metal hypervisor [0130, as pointed out the system only contains hardware and software that can run the virtual machine software.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method Pappu to provide a virtual machine environment for the apparatus.
As per claim 12, Sharfi does not teach the hypervisor includes a Type 2 hypervisor.
However, Pappu teaches the hypervisor includes a Type 2 hypervisor [0130, end user will have minimum requirement to run the virtual machine].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method Pappu to provide a virtual machine environment for the apparatus
As per claim 13, Sharfi does not teach the hypervisor is configured to execute at least an operating system.
However, Pappu teaches the hypervisor is configured to execute at least an operating system [0130, where the virtual machine can have its own operating system].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method Pappu to provide a virtual machine environment for the apparatus
As per claim 18, Sharfi teaches a virtual-path cross-connect controller card [0011, interconnect that con connect all the modules together. For example, FIGS. 8, and 9 show schematics of typical network architectures for units that include daisy-chained modules in accordance with the present invention].
As per claim 20, Sharfi teaches at least a high-density input and output port communicatively connected to the graphical processing unit and the general- purpose processor [0034, fiber optic port that can connect modules together].
As per claim 21, Sharfi teaches the general-purpose processor comprises an advanced RISC machine processor [0083, 0088, processor module with any architecture can be used].
As per claim 22, Sharfi teaches the general-purpose processor comprises a system on module design [0026, fig. 5-7, shown the system module design].
As per claim 23, Sharfi does not teach operate on an edge computing system; and execute, using parallel processing of the graphical processing unit, at least a machine learning model.
However, Pappu teaches operate on an edge computing system [0166, fig. 5, edge system which process data based on specific function running on one system].
and execute, using parallel processing of the graphical processing unit, at least a machine learning model [0171, machine learning architecture].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method Pappu to user machine learning to provide some operation of the system.
As per claim 24, Sharfi does not teach the at least a machine learning model is configured to process visual data to enable visual-based navigation capabilities within an edge computing environment.
However, Pappu teaches the at least a machine learning model is configured to process visual data to enable visual-based navigation capabilities within an edge computing environment [0171-0172, machine learning that use modeling to process the input for a desired output].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the design of Sharfi to include the method Pappu to user machine learning to provide some operation of the system.
As per claim 25, Sharfi teaches the apparatus is communicatively connected to at least a peripheral device, wherein the peripheral device comprises a gigabit multimedia serial link camera [0082, as shown in figure 18, 100Gigabit Ethernet port for high-speed data processing].
As per claim 26, Sharfi teaches one or more aspects of open mission systems by utilizing standardized interfaces, wherein the apparatus applies the one or more aspects of the open mission systems to Kubernetes orchestration to manage and deploy modular system components [0087, rugged design for extreme environment field deployment].
Claim 6-8, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sharfi (US Patent Application 20230097002) in the view of Pappu (US Patent Application 20230109990) and in the view of Macha (US Patent Application 20230147827).
As per claim 6, Sharfi and Pappu do not teach the memory comprises a boot partition.
However, Macha teaches the memory comprises a boot partition [0090, fig. 11, monitoring boot partition of the system].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Sharfi and Pappu to include the method of Macha to enable partition to boot the system.
As per claim 7, Sharfi and Pappu do not teach the boot partition comprises a trusted boot module.
However, Macha teaches the boot partition comprises a trusted boot module [0090, fig. 11 trusted boot].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Sharfi and Pappu to include the method of Macha to enable partition for trusted boot of the system.
As per claim 8, Sharfi and Pappu do not teach the trusted boot module is configured to perform a secure proof protocol.
However, Macha teaches the trusted boot module is configured to perform a secure proof protocol [0090, secure boot through certificate].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Sharfi and Pappu to include the method of Macha to perform secure boot using boot certificate.
As per claim 17, Sharfi and Pappu do not teach the hardware comprises a trusted platform module.
However, Macha teaches the hardware comprises a trusted platform module [0046-0047, trusted platform module for security].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Sharfi and Pappu to include the method of Macha to use a trusted platform module chip to enable the system to be more secure.
As per claim 19, Sharfi and Pappu do not teach the memory contains instructions configuring the at least a core to verify a compliance of the hardware apparatus with at least a pre- determined safety standard from a trusted repository by monitoring an adherence of the hardware apparatus to the pre-defined operational rule.
However, Macha teaches the memory contains instructions configuring the at least a core to verify a compliance of the hardware apparatus with at least a pre- determined safety standard from a trusted repository by monitoring an adherence of the hardware apparatus to the pre-defined operational rule [0030, 0036, policy rules to manage the system security].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the designs of Sharfi and Pappu to include the method of Macha to use specific rules to manage the system security.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cheng (US 20210373600) teaches expansion electronic device.
Khan (US 20220091870) teaches near-hitless upgrade or fast boot with virtualized hardware.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VOLVICK DEROSE whose telephone number is (571)272-6260. The examiner can normally be reached on Monday-Friday 9AM-6PM.
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/VOLVICK DEROSE/Primary Examiner, Art Unit 2176
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