DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/17/26 have been fully considered but they are not persuasive.
Applicant argues that Park does not teach “plurality of peak current detection messages” and points out that the “messages” being different types of messages as disclosed par. 34 of the specification. The claim requires plurality of peak current detection messages [signals] associated with plurality of peak current events. The claim does not require the messages are of different types as argued. Claim 1 is reproduced below to highlight features in dispute
“…PMIC configured to manage a plurality of peak current events associated with the processing engine based on a plurality of peak current detection messages to generate a management plan, and configured to mitigate the plurality of peak current events using a plurality of mitigation actions from the management plan” (emphasis added).
Applicant’s argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., type of message as specified in par. 34 ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Park teaches a power management integrated circuit PMIC (Fig. 3, 180) coupled to the processing engine to manage peak current events [shown in Fig.1 ]. Park discloses [par. 23 and 27] “ peak dynamic power (“PDP”) management module(s) seek to monitor and manage a peak dynamic current budget in view of real-time assessments of a power supply level, voltage level(s) and a leakage current level(s)]… leakage power consumption changes slowly whereas dynamic power consumption changes quickly based on workload changes. As can further be seen in the exemplary graph 97, the total current demand may peak at levels above the maximum current supply (illustrated as 12A in the FIG. 1 graph 97) if not managed”
Thus Park teaches the PMIC configured to manage a plurality of peak current events associated with the processing engine based on a plurality of peak current detection messages (pars. 34: " one or more temperature sensors 157A are configured to sense operating temperatures (such as junction temperatures) associated with the various function blocks and generate signals, to monitor module 114, indicative of those temperatures"; 37: " the monitor module 114 monitors a signal from one or more temperature sensors 157A to track leakage power consumption levels of active components associated with the various rails. In addition to the temperature sensors 157A, monitor module 1 14 may also monitor sensors 157B (not shown) associated with the PMIC 180 to recognize parameters useful for determining an actual provided power supply level. The monitor module 114 may subsequently communicate with the PDP module 101 to relay the monitored data indicative of active leakage power consumption of functional blocks residing on the SoC 102 and actual power supply levels available from the PMIC 180") to generate a management plan (par. 37: " the PDP module 101 may use the monitored data to determine an actual available power supply for allocation to dynamic power consumption by the various function blocks and then adjust a peak dynamic current threshold based on the determination. An adjusted peak dynamic current threshold may be used to trigger a dynamic control and voltage scaling (DCVS) module 26 to throttle the function blocks to optimal workload processing levels"), and configured to mitigate the plurality of peak current events using a plurality of mitigation actions from the management plan (see again par. 37].
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 6-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Park US 20160179164 A1.
Regarding claim 1, Park teaches an apparatus [Fig. 3, device 100] comprising
a processing engine [SoC having Cores/Functional blocks 1-b , par. 33] configured to perform general purpose processing; and
a power management integrated circuit (PMIC ) coupled to the processing engine [par. 23-24, peak power management (PDP) including PMIC 180 to monitor, analyze and manage a power supply], the PMIC configured to manage a plurality of peak current events associated with the processing engine based on a plurality of peak current detection messages to generate a management plan [par. 3 and 25, power request increase causes a current threshold to increase; par. 5-6; adjusted threshold may then be used to trigger adjustments to throttling; par. See also par. 34-37, sensors 157 are configured to generate signals. Par. 51 the monitor module 114 communicates with multiple operational sensors 157 distributed throughout the on-chip system 102 and/or PMIC 180 and with the CPU 110 of the PCD 100 as well as with the PDP module 101]
configured to mitigate the plurality of peak current events using a plurality of mitigation actions from the management plan [par. 45-46, DCVS module 26 may be triggered to adjust down frequency settings and/or voltage settings of one or more function blocks to maintain peak current level within a dynamic current budget to be within budget. See also par 21,23, 27 33-34]
Claim 2. Park teaches the apparatus of claim 1, wherein the PMIC is further configured to send the plurality of peak current detection messages based on a detection of the plurality of peak current events [ Fig. 3 and 5; par. 35, the monitor module 114 and/or certain sensors 157 may be included in the PMIC 180. par. 34-37, sensors sending signals, par. 41, PMIC may include its own monitor module].
Claim 3. Park teaches the apparatus of claim 1, wherein the processing engine is further configured to send the plurality of peak current detection messages based on a detection of the plurality of peak current events [ Fig. 3 and 5; Par. 51 the monitor module 114 communicates with multiple operational sensors 157 distributed throughout SoC 102. Par. 34, 37, 45-46, workload of the power domain exceeds the dynamic power budget and trigger signal provided to the DCVS module, par. 35, monitor module 114 and PDP module 101 are residing on the SoC 102]
Claim 6. Park teaches the apparatus of claim 2, further comprising a current sensor residing within the processing engine the current sensor configured to compare a monitored current load of the processing engine with a current threshold [ Fig. 3 and 5; par. 45-46, 51, workload of the power domain exceeds the dynamic power budget, a trigger signal generated to the DCVS module 26; sensors 157 distributed throughout SoC 102; the dynamic power budget threshold may be associated with any unit of electrical measurement indicative of power consumption such as, but not limited to, watts or amperes, i.e, current sensor]
Claim 7. Park teaches the apparatus of claim 3, repeats the same limitation of claim 6 and therefore rejected accordingly.
Regarding claim 8. Park teaches a method comprising: managing a plurality of peak current events based on a plurality of peak current detection messages to generate a management plan; and mitigating the plurality of peak current events using a plurality of mitigation actions from the management plan as disclosed in claim 1 above.
Claim 9. Park teaches the method of claim 8, further comprising sending a plurality of trigger signals based on the plurality of mitigation actions [par. 5-6; adjusted threshold may then be used to trigger adjustments to throttling; See also par. 34-37 and 45-46].
Claim 10. Park teaches the method of claim 9, further comprising triggering the plurality of mitigation actions based on one or more overcurrent conditions conveyed on the plurality of peak current detection messages [Fig. 1 and 3, par, 34 and 39, use current sensors to monitor the power rails 190] Fig. 3 and 5; par. 45-46, 51, workload of the power domain exceeds the dynamic power budget, a trigger signal generated to the DCVS module 26; sensors 157 distributed throughout SoC 102; the dynamic power budget threshold may be associated with any unit of electrical measurement indicative of power consumption such as, but not limited to, watts or amperes, i.e, current sensor].
Claim 11. Park teaches the method of claim 8, wherein the management plan includes a plurality of configuration tables used to determine the plurality of mitigation actions [ Fig. 2, 4 , 8 par. 38-39, lookup table 24, par. 71-75, logic 260-270 and system file 290]
Claim 12. Park teaches the method of claim 11, wherein the plurality of configuration tables includes a mitigation prioritization table or a mitigation duration table [ Fig. 2 and 4 and their description in par. 29-32 and 38-39; dynamic power budget calculation derived from an estimate of the actual leakage power levels, the PDP module 101 may query a lookup table 24 to determine threshold settings for the various function blocks]
Claim 13. Park teaches the method of claim 8, wherein the plurality of mitigation actions includes an adjustment of a dynamic clock voltage scaling (DCVS) setpoint, a clock frequency reduction, an architectural instruction throttle or a processing engine toggle [par. 46, DCVS module 26 may be triggered to adjust down frequency settings and/or voltage settings of one or more function blocks. Par. 37 adjusted peak dynamic current threshold may be used to to throttle the function blocks to optimal workload processing levels, See also Fig. 5, par, 41-45]
Claim 14. Park teaches the method of claim 8, further comprising sending the plurality of peak current detection messages based on a detection of the plurality of peak current events [ Fig. 3 and 5; par. 34 and 37 sensors 157 sending monitoring signals]
Claim 15. Park teaches the method of claim 14, further comprising detecting the plurality of peak current events while executing one or more processing tasks using a plurality of processing engines to generate the detection of the plurality of peak current events [par. 4, 34-37, sensors 157A are configured to sense operating temperatures associated with the various function blocks. Fig. 3 and 5; par. 45-46, 51, workload of the power domain exceeds the dynamic power budget, a trigger signal generated to the DCVS module 26; sensors 157 distributed throughout SoC 102; the dynamic power budget threshold may be associated with any unit of electrical measurement indicative of power consumption such as, but not limited to, watts or amperes, i.e, current sensor] .
Regarding claim 16. Park teaches an apparatus for peak current mitigation comprising having means for managing a plurality of peak current events based on a plurality of peak current detection messages to generate a management plan; and means for mitigating the plurality of peak current events using a plurality of mitigation actions from the management plan as disclosed in claim 1 above.
Claim 17. Park teaches the apparatus of claim 16, further comprising means for sending the plurality of peak current detection messages based on a detection of the plurality of peak current events [Fig. 1 and 3, par, 34-39, current sensors sends temperatures and current signals ]
Claim 18. Park teaches the apparatus of claim 17, further comprising means for detecting the plurality of peak current events while executing one or more processing tasks using a plurality of processing engines to generate the detection of the plurality of peak current events .[par. 4, 34-37, sensors 157A are configured to sense operating temperatures associated with the various function blocks; power consumption of the function blocks and actual, near real-time power supply levels].
Claim 19. Park teaches the apparatus of claim 18, further comprising: means for sending a plurality of trigger signals based on the plurality of mitigation actions [ Fig. 1, 3 and 7, par, 34 and 39, use current sensors in an effort to monitor the power rails 190]; and
means for triggering the plurality of mitigation actions based on one or more overcurrent conditions conveyed on the plurality of peak current detection messages. [par. 5-6; adjusted threshold may then be used to trigger adjustments to throttling; See also par. 34-37 and 45-46].
Claim 20. Park teaches the apparatus of claim 19 and wherein the plurality of mitigation actions includes an adjustment of a dynamic clock voltage scaling (DCVS) setpoint, a clock frequency reduction, an architectural instruction throttle or a processing engine toggle [ par. 46, DCVS module 26 may be triggered to adjust down frequency settings and/or voltage settings of one or more function blocks. Par. 37 adjusted peak dynamic current threshold may be used to to throttle the function blocks to optimal workload processing levels, See also Fig. 5, par, 41-45].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Varma 20140195828 A1
Claim 4. Park teaches the apparatus of claim 2. further comprising a current measurement residing within the processing engine , the digital power meter configured to measure a current load demand based on a voltage, a clock frequency, a temperature and a workload of the processing engine. [ Fig. 3 and 5 par. 51, monitor module 114 and sensors 157 distributed throughout the SoC 102 to monitor current consumption rates of the cores and to determine the dynamic current budget; par. 46, the dynamic power budget threshold may be associated with any unit of electrical measurement to indicative of power consumption of a power for the function block(s). The amount of power provided for processing workloads is dictated by the dynamic power budget threshold such that, if the threshold is exceeded, may be triggered to adjust down frequency settings and/or voltage settings of one or more function blocks. Par. 34, sensor 17 provides temperature readings to determine an active leakage current associated with each of the function blocks, current sensors may be used associated with the various function blocks].
Park does not specially teaches a digital power meter (DPM) but does state any type of sensors maybe used by a given embodiment of the solution to deduce leakage power consumption associated with one or more function blocks and/or power supply level and further teaches that the sensor 175 can be on-chip thermal sensors 157A may comprise one or more proportional to absolute temperature (“PTAT”) temperature sensors that are based on vertical PNP structure and are usually dedicated to complementary metal oxide semiconductor (“CMOS”) very large-scale integration (“VLSI”) circuits [par. 56]. Thus, Park teaches the sensor being digital sensor as claimed.
In the alternative, Varma teaches a digital power meter digital power meter generate a power consumption level for the core and communicate this information to a power control unit described below [Varma, par. 17]. It would have been obvious to one having ordinary skill in the art before the effective filing date to utilize the digital power meter as taught by Varma to provide a power measurement for a processor that is highly accurate and enhance energy management and efficiency [Varma, par. 15]
Claim 5. Park teaches the apparatus of claim 3 and repeats the limitation of claim 4 and therefore rejected accordingly.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KIM HUYNH/Primary Patent Examiner,
Art Unit 2176
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