Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj et al. (US 2021/0035627) in view of Warriner (US 2016/0320995).
Regarding claim 1, Tanpairoj discloses a solid state drive configured to be connected to an information processing apparatus, comprising:
an electrically rewritable nonvolatile memory [see paragraph 16; solid state drive (SSD)]; and
a memory controller that accepts a processing command for the nonvolatile memory and performs processing corresponding to the processing command, the memory controller switching between a first processing mode with higher processing power for the nonvolatile memory and a second processing mode with lower processing power than the first processing mode, depending on a value of queue depth (QD) indicating a number of the processing commands issued by the information processing apparatus at a time [see paragraph 14; memory controller accepts commands from incoming write queue, and when queue depth is above a threshold initiates a high performance mode, and when below a threshold initiates a standard performance mode].
Tanpairoj does not expressly disclose the first and second processing modes corresponds to first and second power states.
Warriner discloses a SSD storage device that may operate in a plurality of different power states. Each power state has associated performance metrics that control how the SSD and controller operate (e.g. power state 0 could be considered a high performance mode as it provides the best performance, while power state 0 could be considered a lower performance mode as it provides a lower performance than the other power states) [see Table 1 and paragraphs 14-17].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the power states of Warriner in the system of Tanpairoj.
The motivation for doing so would have been to meet performance and power objectives [see Warriner, paragraphs 14 and 17].
Therefore, it would have been obvious to combine Warriner with Taipairoj for the benefits listed above, to obtain the invention as specified in claims 1 and 6-7.
Claims 6 and 7 recite similar claim limitations as claim 1 and are rejected using the same citations and interpretations as above.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj in view of Warriner and further in view of Sharifie et al. (US 2017/0060422).
Regarding claim 2, the combination of Tanpairoj and Warriner discloses the solid state drive according to claim 1 as described above, including switching to the first processing mode when the value of queue depth is greater than or equal to a predetermined threshold and switches to the second processing mode when the value of queue depth is less than the predetermined threshold [see paragraph 14].
The combination does not expressly disclose the solid state drive is configured to be connected to the information processing apparatus via a peripheral component interconnect-express bus (PCIe); and the memory controller confirms a buffer storage section in response to a reception of a notification indicating that the processing command is stored in the buffer storage section included in the information processing apparatus.
Sharifie discloses a storage system comprising a host device coupled to a memory system via a PCIe interface [see paragraph 18]. The host device sends a notification to the memory device that non-volatile memory commands are available for execution in a non-volatile memory command submission queue and the memory device fetches the commands from the submission queue [see paragraphs 21-23].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the notification teachings of Sharfie in the system of Tanpairoj and Warriner.
The motivation for doing so would have been to allow the memory device to know that commands are waiting to be fetched so that they may be executed on the memory device in a desired order [see Sharifie, paragraph 22].
Therefore, it would have been obvious to combine Sharifie with Tanpairoj and Warriner for the benefits listed above, to obtain the invention as specified in claim 2.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tanpairoj in view of Sharifie and Warriner and further in view of Xiong et al. (US 2023/0350482).
Regarding claim 3, the combination of Tanpairoj, Warriner and Sharifie discloses the solid state drive according to claim 2 as discussed above.
The combination does not expressly disclose the memory controller selects a mode with a lower transfer rate of the PCIe bus than the first processing mode in the second processing mode, and selects a mode with a higher transfer rate of the PCIe bus than the second processing mode in the first processing mode.
Xiong discloses a storage system comprising a host device coupled to the storage system via a PCIe interface [see paragraph 22]. A reduced power consumption mode may be activated on the memory sub-system which can cause the PCIe mode to switch from a PCIe generation 4 (higher transfer rate) to a PCIe generation 3 (lower transfer rate) [see paragraph 39].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the PCIe switching of Xiong in the system of Tanpairoj, Warriner and Sharifie.
The motivation for doing so would have been to reduce power consumption of the memory system while maintaining (or improving) data performance and/or data latency [see Xiong, paragraph 15].
Therefore, it would have been obvious to combine Xiong with Sharifie, Warriner and Tanpairoj for the benefits listed above, to obtain the invention as specified in claims 3-5.
Regarding claim 4, the combination discloses the solid state drive according to claim 3, wherein the memory controller is configured to process the processing commands in parallel by a plurality of threads [see Sharifie, paragraph 49; memory controller may process commands from host in parallel, each different command may be considered a thread], and switches to the first processing mode when at least one of the values of queue depth corresponding to the respective threads stored by the buffer storage section is greater than or equal to the predetermined threshold [see Tanpairoj, paragraph 14; performance mode changed based on queue depth].
Regarding claim 5, the combination discloses an information processing apparatus that incorporates the solid state drive according to claim 4 [see Tanpairoj, system may be incorporated into a computer or mobile device].
Response to Arguments
Applicant’s arguments, filed 3/17/2026, with respect to the rejection(s) of claim(s) 1 and 6-7 under Taipairoj have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Warriner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jeter (US 2018/0074743), Tidwell (US 2019/0094938) – Generally teaches a memory system for dynamically switching between performance states based on a queue depth.
Mukker (US 2021/0109587) – Generally teaches a changing a PCIe transfer rate based on a temperature of storage.
Kim (US 2021/0326059) – Generally teaches adjusting a performance level of a storage device based on an operating temperature.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN BERTRAM/Primary Examiner, Art Unit 2137
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