DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/04/2024 and 07/17/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: element 141 is not found in drawing. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7 and 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20230080684).
With respect to claim 1, Kim discloses a multilayer electronic component (see FIG. 1, element 100), comprising: a body (see FIG. 1, element 110) including a dielectric layer (see FIG. 2, element 111) and internal electrodes (see FIG. 2, elements 121 and 122); and external electrodes (see FIG. 2, elements 131 and 132) disposed on the body, wherein, when an average thickness of the dielectric layer is defined as td μm (see FIG. 2, element td, paragraph 76), the dielectric layer includes secondary phases including Si (see paragraph 46, noting Si), the secondary phases include five or more first secondary phases (see FIG. 2, element td, paragraph 52, noting 4 or more may be six or more first secondary phases), and each of the five or more first secondary phases includes Si (see paragraph 47, noting Si) and has a cross-sectional area of 0.01 μm2 or more within a td μm × td μm region (see paragraph 77 in combination with paragraph 64, noting (0.6μm *0.6μm)=0.36*0.06=0.0216um2) satisfy the claim limitation.
With respect to claim 2, Kim discloses that the secondary phases further include five or less second secondary phases, and each of the second secondary phases includes Si (see paragraph 66, noting Si) and has a cross-sectional area of less than 0.01 μm2 within a 1 μm × 1 μm region (see paragraph 66, noting the reference indicates that in total 70% of the secondary phase to be first secondary phase and 30% roughly to be second secondary phase. As such total amount of area maintained as second secondary phase is roughly 30% of total secondary phases which satisfy the claim limitation).
With respect to claim 7, Kim discloses that the dielectric layer includes a main component that includes a barium titanate (BaTiO3)-based material (see paragraph 71, noting BaTiO3).
With respect to claim 12, Kim discloses td μm is 10.0 μm or less (see paragraph 77, noting thickness of less than 0.6 μm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230080684) in view of Ariizumi et al. (US 20220254570).
With respect to claim 3, Kim teaches the multilayer electronic component of claim 1 (see FIG. 1, element 100).
Kim does not expressly teach that an average atomic percentage of Si in at least one of the secondary phases is 5 at% or more and 20 at% or lower.
Ariizumi, on the other hand, teaches an average atomic percentage of Si in at least one of the secondary phases is 5 at% or more and 20 at% or lower (see paragraph 46, noting the segregation phase having 1.0 atomic % or more is defined as a first segregation phase).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Kim and Ariizumi to form the claimed invention in order to obtain a high density and favorable relative permittivity, specific resistance, and high-temperature load life (see paragraph 6).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230080684) in view of Sueda et al. (US20230386745).
With respect to claim 5, Kim teaches the multilayer electronic component of claim 1 (see FIG. 1, element 100).
Kim does not expressly teach that the dielectric layer includes a plurality of dielectric grains, and an average diameter of the plurality of dielectric grains is 150 nm or more 220 nm or less.
Sueda, on the other hand, teaches the dielectric layer includes a plurality of dielectric grains, and an average diameter of the plurality of dielectric grains is 150 nm or more 220 nm or less (see paragraph 51, noting 0.1um to 2um).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Kim and Sueda to form the claimed invention in order to improve the insulation resistance (IR) and the breakdown dielectric voltage (BDV) (see Sueda paragraph 94).
Claims 6, 8-11 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230080684) in view of Yoon et al. (US20160086735).
With respect to claim 6, Kim teaches the multilayer electronic component of claim 1 (see FIG. 1, element 100).
Kim does not expressly teach that the dielectric layer includes a core-shell dielectric grain including a core and a shell structure surrounding at least a portion of the core, and wherein a diameter of the core is 90 nm or more and 140 nm or less.
Yoon, on the other hand, teaches the dielectric layer includes a core-shell dielectric grain including a core and a shell structure surrounding at least a portion of the core (see FIG. 1, element 1 and element 2), and wherein a diameter of the core is 90 nm or more and 140 nm or less (see paragraph 84, noting 40 nm≦D1≦150 nm).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Kim and Yoon to form the claimed invention in order to obtain high capacitance (see Yoon paragraph 84).
With respect to claim 8, the combined teachings of Kim and Yoon teach that the dielectric layer further includes a first sub-component element, wherein the first sub-component element is one or more of Mn, V, Cr, Fe, Co, Ni, Cu, Co, and Zn (see Yoon paragraph 45), and wherein a number of moles of the first sub-component element based on 100 moles of Ti included in the dielectric layer is 0.4 moles or more and 0.8 moles or less (see Yoon paragraph 46, noting 0.1 to 2.0 mol % on the basis of 100 mol % of the base powder).
With respect to claim 9, the combined teachings of Kim and Yoon teach that the dielectric layer further includes a second sub-component element, wherein the second sub-component element is Mg (see Yoon paragraph 53), and wherein a number of moles of the second sub-component elements based on 100 moles of Ti included in the dielectric layer is more than 0 moles and 1 mole or less (see Yoon paragraph 54, noting 0.0 to 0.5 mol % on the basis of 100 mol % of the base powder).
With respect to claim 10, the combined teachings of Kim and Yoon teach that the dielectric layer further includes third sub-component elements, wherein the third sub-component elements are rare earth elements (see Yoon paragraph 58), and wherein a number of moles of the third sub-component elements based on 100 moles of Ti included in the dielectric layer is 2.5 moles or more 3.5 moles or less (see Yoon paragraph 59, noting 0.0 to 4.0 mol % on the basis of 100 mol % of the base powder).
With respect to claim 11, the combined teachings of Kim and Yoon teach that the dielectric layer further includes a fourth sub-component element, wherein the fourth sub-component element is Si (see Yoon paragraph 74), and wherein a number of moles of the fourth sub-component element based on 100 moles of Ti included in the dielectric layer is 0.8 moles or more and 2.0 moles or less (see Yoon paragraph 75, noting 0.0 to 4.0 mol % on the basis of 100 mol % of the base powder).
With respect to claim 15, the combined teachings of Kim and Yoon teach that the first sub-component element includes Mn and V (see Yoon paragraph 45).
With respect to claim 16, the combined teachings of Kim and Yoon teach that the rare earth elements include Dy and Tb (see Yoon paragraph 58).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230080684) in view of Hiramatsu et al. (US20060139845).
With respect to claim 13, Kim teaches the multilayer electronic component of claim 1 (see FIG. 1, element 100).
Kim does not expressly teach that the multilayer electronic component satisfies a mean time to failure (MTTF) of more than 100 hours under a temperature of 150°C and an electric field of 10 V/μm.
Hiramatsu, on the other hand, teaches the multilayer electronic component satisfies a mean time to failure (MTTF) of more than 100 hours under a temperature of 150°C and an electric field of 10 V/μm (see paragraph 58).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Kim and Hiramatsu to obtain secure the reliability of the resulting laminated ceramic capacitor (see Hiramatsu paragraph 12-13).
With respect to claim 14, the combined teachings of Kim and Hiramatsu teach that the multilayer electronic component satisfies at least one of properties: room temperature dielectric constant is 2200 or more, dielectric loss is 10% or lower, insulation resistance at 150°C is 1.0E+6 Ω or more, a capacitance change rate at -55°C to 125°C based on capacitance at 25° is 15% or lower, a DC-bias change rate under electric field of 10 V/μm is 70% or lower, and mean time to failure (MTTF) under temperature of 150°C and electric field of 10 V/μm is 100 hours or more (see Hiramatsu paragraph 58).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Yoon, as applied to claim 16 above, and further in view of Hiramatsu et al. (US20060139845).
With respect to claim 17, Kim teaches the multilayer electronic component of claim 16 (see FIG. 1, element 100).
Kim does not expressly teach that the multilayer electronic component satisfies: room temperature dielectric constant of 2200 or more, dielectric loss of 10% or lower, insulation resistance at 150°C of 1.0E+6 Ω or more, a capacitance change rate at -55°C to 125°C based on capacitance at 25° of 15% or lower, a DC-bias change rate under electric field of 10 V/μm of 70% or lower, and mean time to failure (MTTF) under temperature of 150°C and electric field of 10 V/μm of 100 hours or more.
Hiramatsu, on the other hand, teaches the multilayer electronic component satisfies: room temperature dielectric constant of 2200 or more, dielectric loss of 10% or lower, insulation resistance at 150°C of 1.0E+6 Ω or more, a capacitance change rate at -55°C to 125°C based on capacitance at 25° of 15% or lower, a DC-bias change rate under electric field of 10 V/μm of 70% or lower, and mean time to failure (MTTF) under temperature of 150°C and electric field of 10 V/μm of 100 hours or more (see Hiramatsu paragraph 58).
Accordingly, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Kim, Yoon and Hiramatsu to obtain secure the reliability of the resulting laminated ceramic capacitor (see Hiramatsu paragraph 12-13).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: with respect to claim 4, the prior art fails to teach, or fairly suggest, the limitations of claim 4, the dielectric layer includes a core-shell dielectric grain including a core and a shell structure surrounding at least a portion of the core, and wherein an average atomic percentage of Si in at least one of the secondary phases is higher than an average atomic percentage of Si in the shell, when taken in conjunction with the limitations of base claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESTHER N LIAN whose telephone number is (571)272-5726. The examiner can normally be reached Monday-Friday 8:00 - 5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ESTHER N LIAN/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
Prosecution Insights